Commit 2f8d8548 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-next-2023-12-07' of git://anongit.freedesktop.org/drm/drm-intel into drm-next 



- Improve display debug msgs and other general clean-ups (Ville, Rahuul)
- PSR fixes and improvements around selective fetch (Jouni, Ville)
- Remove FBC restrictions for Xe2LPD displays (Vinod)
- Skip some timing checks on BXT/GLK DSI transcoders (Ville)
- DP MST Fixes (Ville)
- Correct the input parameter on _intel_dsb_commit (heminhong)
- Fix IP version of the display WAs (Bala)
- DGFX uses direct VBT pin mapping (Clint)
- Proper handling of bool on PIPE_CONF_CHECK macros (Jani)
- Skip state verification with TBT-ALT mod (Mika Kahona)
- General organization of display code for reusage with Xe
  (Jouni, Luca, Jani, Maarten)
- Squelch a sparse warning (Jani)
- Don't use "proxy" headers (Andy Shevchenko)
- Use devm_gpiod_get() for all GPIOs (Hans)
- Fix ADL+ tiled plane stride (Ville)
- Use octal permissions in display debugfs (Jani)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/ZXIWG6bRYaUw0w6-@intel.com
parents 5edfd7d9 10690b8a

drivers/gpu/drm/i915/Makefile

+3 −1
Original line number Diff line number Diff line
@@ -280,6 +280,7 @@ i915-y += \ 
	display/intel_dsb.o \

	display/intel_dsb_buffer.o \

	display/intel_fb.o \

	display/intel_fb_bo.o \

	display/intel_fb_pin.o \

	display/intel_fbc.o \

	display/intel_fdi.o \
@@ -318,7 +319,8 @@ i915-$(CONFIG_ACPI) += \ 
	display/intel_acpi.o \

	display/intel_opregion.o

i915-$(CONFIG_DRM_FBDEV_EMULATION) += \

	display/intel_fbdev.o

	display/intel_fbdev.o \

	display/intel_fbdev_fb.o

i915-$(CONFIG_DEBUG_FS) += \

	display/intel_display_debugfs.o \

	display/intel_display_debugfs_params.o \

drivers/gpu/drm/i915/display/i9xx_wm.c

+4 −4
Original line number Diff line number Diff line
@@ -2477,7 +2477,7 @@ static unsigned int ilk_plane_wm_max(const struct drm_i915_private *dev_priv, 
		 * FIFO size is only half of the self

		 * refresh FIFO size on ILK/SNB.

		 */

		if (DISPLAY_VER(dev_priv) <= 6)

		if (DISPLAY_VER(dev_priv) < 7)

			fifo_size /= 2;

	}
@@ -2818,7 +2818,7 @@ static int ilk_compute_pipe_wm(struct intel_atomic_state *state, 
	usable_level = dev_priv->display.wm.num_levels - 1;



	/* ILK/SNB: LP2+ watermarks only w/o sprites */

	if (DISPLAY_VER(dev_priv) <= 6 && pipe_wm->sprites_enabled)

	if (DISPLAY_VER(dev_priv) < 7 && pipe_wm->sprites_enabled)

		usable_level = 1;



	/* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
@@ -2961,7 +2961,7 @@ static void ilk_wm_merge(struct drm_i915_private *dev_priv, 
	int last_enabled_level = num_levels - 1;



	/* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */

	if ((DISPLAY_VER(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) &&

	if ((DISPLAY_VER(dev_priv) < 7 || IS_IVYBRIDGE(dev_priv)) &&

	    config->num_pipes_active > 1)

		last_enabled_level = 0;
@@ -3060,7 +3060,7 @@ static void ilk_compute_wm_results(struct drm_i915_private *dev_priv, 
		 * Always set WM_LP_SPRITE_EN when spr_val != 0, even if the

		 * level is disabled. Doing otherwise could cause underruns.

		 */

		if (DISPLAY_VER(dev_priv) <= 6 && r->spr_val) {

		if (DISPLAY_VER(dev_priv) < 7 && r->spr_val) {

			drm_WARN_ON(&dev_priv->drm, wm_lp != 1);

			results->wm_lp_spr[wm_lp - 1] |= WM_LP_SPRITE_ENABLE;

		}

drivers/gpu/drm/i915/display/icl_dsi.c

+7 −0
Original line number Diff line number Diff line
@@ -1440,6 +1440,13 @@ static void gen11_dsi_post_disable(struct intel_atomic_state *state, 
static enum drm_mode_status gen11_dsi_mode_valid(struct drm_connector *connector,

						 struct drm_display_mode *mode)

{

	struct drm_i915_private *i915 = to_i915(connector->dev);

	enum drm_mode_status status;



	status = intel_cpu_transcoder_mode_valid(i915, mode);

	if (status != MODE_OK)

		return status;



	/* FIXME: DSC? */

	return intel_dsi_mode_valid(connector, mode);

}

drivers/gpu/drm/i915/display/intel_bios.c

+3 −2
Original line number Diff line number Diff line
@@ -2201,6 +2201,9 @@ static u8 map_ddc_pin(struct drm_i915_private *i915, u8 vbt_pin) 
	const u8 *ddc_pin_map;

	int i, n_entries;



	if (IS_DGFX(i915))

		return vbt_pin;



	if (INTEL_PCH_TYPE(i915) >= PCH_LNL || HAS_PCH_MTP(i915) ||

	    IS_ALDERLAKE_P(i915)) {

		ddc_pin_map = adlp_ddc_pin_map;
@@ -2208,8 +2211,6 @@ static u8 map_ddc_pin(struct drm_i915_private *i915, u8 vbt_pin) 
	} else if (IS_ALDERLAKE_S(i915)) {

		ddc_pin_map = adls_ddc_pin_map;

		n_entries = ARRAY_SIZE(adls_ddc_pin_map);

	} else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) {

		return vbt_pin;

	} else if (IS_ROCKETLAKE(i915) && INTEL_PCH_TYPE(i915) == PCH_TGP) {

		ddc_pin_map = rkl_pch_tgp_ddc_pin_map;

		n_entries = ARRAY_SIZE(rkl_pch_tgp_ddc_pin_map);

drivers/gpu/drm/i915/display/intel_bw.c

+4 −3
Original line number Diff line number Diff line
@@ -87,7 +87,8 @@ static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv, 
		return ret;



	dclk = val & 0xffff;

	sp->dclk = DIV_ROUND_UP((16667 * dclk) + (DISPLAY_VER(dev_priv) > 11 ? 500 : 0), 1000);

	sp->dclk = DIV_ROUND_UP((16667 * dclk) + (DISPLAY_VER(dev_priv) >= 12 ? 500 : 0),

				1000);

	sp->t_rp = (val & 0xff0000) >> 16;

	sp->t_rcd = (val & 0xff000000) >> 24;
@@ -480,7 +481,7 @@ static int tgl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel 
	if (num_channels < qi.max_numchannels && DISPLAY_VER(dev_priv) >= 12)

		qi.deinterleave = max(DIV_ROUND_UP(qi.deinterleave, 2), 1);



	if (DISPLAY_VER(dev_priv) > 11 && num_channels > qi.max_numchannels)

	if (DISPLAY_VER(dev_priv) >= 12 && num_channels > qi.max_numchannels)

		drm_warn(&dev_priv->drm, "Number of channels exceeds max number of channels.");

	if (qi.max_numchannels != 0)

		num_channels = min_t(u8, num_channels, qi.max_numchannels);
@@ -897,7 +898,7 @@ static int icl_find_qgv_points(struct drm_i915_private *i915, 
		unsigned int idx;

		unsigned int max_data_rate;



		if (DISPLAY_VER(i915) > 11)

		if (DISPLAY_VER(i915) >= 12)

			idx = tgl_max_bw_index(i915, num_active_planes, i);

		else

			idx = icl_max_bw_index(i915, num_active_planes, i);