Commit 30c0267f authored by Dapeng Mi's avatar Dapeng Mi Committed by Sean Christopherson
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KVM: x86/pmu: Use BIT_ULL() instead of open coded equivalents 



Replace a variety of "1ull << N" and "(u64)1 << N" snippets with BIT_ULL()
in the PMU code.

No functional change intended.

Signed-off-by: default avatarDapeng Mi <dapeng1.mi@linux.intel.com>
[sean: split to separate patch, write changelog]
Tested-by: default avatarXudong Hao <xudong.hao@intel.com>
Link: https://lore.kernel.org/r/20250806195706.1650976-30-seanjc@google.com


Signed-off-by: default avatarSean Christopherson <seanjc@google.com>
parent 2bff2edf

arch/x86/kvm/svm/pmu.c

+2 −2
Original line number Diff line number Diff line
@@ -200,11 +200,11 @@ static void amd_pmu_refresh(struct kvm_vcpu *vcpu) 
					 kvm_pmu_cap.num_counters_gp);



	if (pmu->version > 1) {

		pmu->global_ctrl_rsvd = ~((1ull << pmu->nr_arch_gp_counters) - 1);

		pmu->global_ctrl_rsvd = ~(BIT_ULL(pmu->nr_arch_gp_counters) - 1);

		pmu->global_status_rsvd = pmu->global_ctrl_rsvd;

	}



	pmu->counter_bitmask[KVM_PMC_GP] = ((u64)1 << 48) - 1;

	pmu->counter_bitmask[KVM_PMC_GP] = BIT_ULL(48) - 1;

	pmu->reserved_bits = 0xfffffff000280000ull;

	pmu->raw_event_mask = AMD64_RAW_EVENT_MASK;

	/* not applicable to AMD; but clean them to prevent any fall out */

arch/x86/kvm/vmx/pmu_intel.c

+6 −9
Original line number Diff line number Diff line
@@ -536,11 +536,10 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu) 
					 kvm_pmu_cap.num_counters_gp);

	eax.split.bit_width = min_t(int, eax.split.bit_width,

				    kvm_pmu_cap.bit_width_gp);

	pmu->counter_bitmask[KVM_PMC_GP] = ((u64)1 << eax.split.bit_width) - 1;

	pmu->counter_bitmask[KVM_PMC_GP] = BIT_ULL(eax.split.bit_width) - 1;

	eax.split.mask_length = min_t(int, eax.split.mask_length,

				      kvm_pmu_cap.events_mask_len);

	pmu->available_event_types = ~entry->ebx &

					((1ull << eax.split.mask_length) - 1);

	pmu->available_event_types = ~entry->ebx & (BIT_ULL(eax.split.mask_length) - 1);



	if (pmu->version == 1) {

		pmu->nr_arch_fixed_counters = 0;
@@ -549,16 +548,15 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu) 
						    kvm_pmu_cap.num_counters_fixed);

		edx.split.bit_width_fixed = min_t(int, edx.split.bit_width_fixed,

						  kvm_pmu_cap.bit_width_fixed);

		pmu->counter_bitmask[KVM_PMC_FIXED] =

			((u64)1 << edx.split.bit_width_fixed) - 1;

		pmu->counter_bitmask[KVM_PMC_FIXED] = BIT_ULL(edx.split.bit_width_fixed) - 1;

	}



	intel_pmu_enable_fixed_counter_bits(pmu, INTEL_FIXED_0_KERNEL |

						 INTEL_FIXED_0_USER |

						 INTEL_FIXED_0_ENABLE_PMI);



	counter_rsvd = ~(((1ull << pmu->nr_arch_gp_counters) - 1) |

		(((1ull << pmu->nr_arch_fixed_counters) - 1) << KVM_FIXED_PMC_BASE_IDX));

	counter_rsvd = ~((BIT_ULL(pmu->nr_arch_gp_counters) - 1) |

			 ((BIT_ULL(pmu->nr_arch_fixed_counters) - 1) << KVM_FIXED_PMC_BASE_IDX));

	pmu->global_ctrl_rsvd = counter_rsvd;



	/*
@@ -603,8 +601,7 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu) 
			pmu->pebs_data_cfg_rsvd = ~0xff00000full;

			intel_pmu_enable_fixed_counter_bits(pmu, ICL_FIXED_0_ADAPTIVE);

		} else {

			pmu->pebs_enable_rsvd =

				~((1ull << pmu->nr_arch_gp_counters) - 1);

			pmu->pebs_enable_rsvd = ~(BIT_ULL(pmu->nr_arch_gp_counters) - 1);

		}

	}

}