Commit 31062ea8 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'samsung-clk-6.13' of... 

Merge tag 'samsung-clk-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into clk-samsung

Pull Samsung SoC clk driver updates from Krzysztof Kozlowski:

 - Tesla FSD: Move number of clocks from DT binding headers to driver,
   because these are not an ABI and might change while finishing support
   for the hardware.

 - ExynosAutov920: Add clock controller drivers for PERIC1, MISC, HSI0
   and HSI1.  Context of patch depends on a fix from fixes branch, thus
   pull in my earlier pull request with fixes.

 - Google GS101: Do not disable UFS host controller clocks, ever,
   because gating them does not work well with UFS sleep/power savings.
   Downstream does not gate them via OS, but uses hardware feature -
   Automatic Clock Gating - which is not yet supported in upstream.

 - Exynos8895: New SoC with initial support for clock controllers:
   FSYS0/1, PERIC0/1, PERIS and TOP.

* tag 'samsung-clk-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  clk: samsung: Introduce Exynos8895 clock driver
  clk: samsung: clk-pll: Add support for pll_{1051x,1052x}
  dt-bindings: clock: samsung: Add Exynos8895 SoC
  clk: samsung: gs101: make all ufs related clocks critical
  clk: samsung: exynosautov920: add peric1, misc and hsi0/1 clock support
  dt-bindings: clock: exynosautov920: add peric1, misc and hsi0/1 clock definitions
  clk: samsung: Fix out-of-bound access of of_match_node()
  dt-bindings: clock: samsung: remove define with number of clocks for FSD
  clk: samsung: fsd: do not define number of clocks in bindings
  clk: samsung: Fix errors reported by checkpatch
  clk: samsung: Fix block comment style warnings reported by checkpatch
parents 9852d85e 9174fac3

Documentation/devicetree/bindings/clock/samsung,exynos8895-clock.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/samsung,exynos8895-clock.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Samsung Exynos8895 SoC clock controller



maintainers:

  - Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>

  - Chanwoo Choi <cw00.choi@samsung.com>

  - Krzysztof Kozlowski <krzk@kernel.org>



description: |

  Exynos8895 clock controller is comprised of several CMU units, generating

  clocks for different domains. Those CMU units are modeled as separate device

  tree nodes, and might depend on each other. The root clock in that root tree

  is an external clock: OSCCLK (26 MHz). This external clock must be defined

  as a fixed-rate clock in dts.



  CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and

  dividers; all other clocks of function blocks (other CMUs) are usually

  derived from CMU_TOP.



  Each clock is assigned an identifier and client nodes can use this identifier

  to specify the clock which they consume. All clocks available for usage

  in clock consumer nodes are defined as preprocessor macros in

  'include/dt-bindings/clock/samsung,exynos8895.h' header.



properties:

  compatible:

    enum:

      - samsung,exynos8895-cmu-fsys0

      - samsung,exynos8895-cmu-fsys1

      - samsung,exynos8895-cmu-peric0

      - samsung,exynos8895-cmu-peric1

      - samsung,exynos8895-cmu-peris

      - samsung,exynos8895-cmu-top



  clocks:

    minItems: 1

    maxItems: 16



  clock-names:

    minItems: 1

    maxItems: 16



  "#clock-cells":

    const: 1



  reg:

    maxItems: 1



required:

  - compatible

  - clocks

  - clock-names

  - reg

  - "#clock-cells"



allOf:

  - if:

      properties:

        compatible:

          contains:

            const: samsung,exynos8895-cmu-fsys0



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (26 MHz)

            - description: CMU_FSYS0 BUS clock (from CMU_TOP)

            - description: CMU_FSYS0 DPGTC clock (from CMU_TOP)

            - description: CMU_FSYS0 MMC_EMBD clock (from CMU_TOP)

            - description: CMU_FSYS0 UFS_EMBD clock (from CMU_TOP)

            - description: CMU_FSYS0 USBDRD30 clock (from CMU_TOP)



        clock-names:

          items:

            - const: oscclk

            - const: bus

            - const: dpgtc

            - const: mmc

            - const: ufs

            - const: usbdrd30



  - if:

      properties:

        compatible:

          contains:

            const: samsung,exynos8895-cmu-fsys1



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (26 MHz)

            - description: CMU_FSYS1 BUS clock (from CMU_TOP)

            - description: CMU_FSYS1 PCIE clock (from CMU_TOP)

            - description: CMU_FSYS1 UFS_CARD clock (from CMU_TOP)

            - description: CMU_FSYS1 MMC_CARD clock (from CMU_TOP)



        clock-names:

          items:

            - const: oscclk

            - const: bus

            - const: pcie

            - const: ufs

            - const: mmc



  - if:

      properties:

        compatible:

          contains:

            const: samsung,exynos8895-cmu-peric0



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (26 MHz)

            - description: CMU_PERIC0 BUS clock (from CMU_TOP)

            - description: CMU_PERIC0 UART_DBG clock (from CMU_TOP)

            - description: CMU_PERIC0 USI00 clock (from CMU_TOP)

            - description: CMU_PERIC0 USI01 clock (from CMU_TOP)

            - description: CMU_PERIC0 USI02 clock (from CMU_TOP)

            - description: CMU_PERIC0 USI03 clock (from CMU_TOP)



        clock-names:

          items:

            - const: oscclk

            - const: bus

            - const: uart

            - const: usi0

            - const: usi1

            - const: usi2

            - const: usi3



  - if:

      properties:

        compatible:

          contains:

            const: samsung,exynos8895-cmu-peric1



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (26 MHz)

            - description: CMU_PERIC1 BUS clock (from CMU_TOP)

            - description: CMU_PERIC1 SPEEDY2 clock (from CMU_TOP)

            - description: CMU_PERIC1 SPI_CAM0 clock (from CMU_TOP)

            - description: CMU_PERIC1 SPI_CAM1 clock (from CMU_TOP)

            - description: CMU_PERIC1 UART_BT clock (from CMU_TOP)

            - description: CMU_PERIC1 USI04 clock (from CMU_TOP)

            - description: CMU_PERIC1 USI05 clock (from CMU_TOP)

            - description: CMU_PERIC1 USI06 clock (from CMU_TOP)

            - description: CMU_PERIC1 USI07 clock (from CMU_TOP)

            - description: CMU_PERIC1 USI08 clock (from CMU_TOP)

            - description: CMU_PERIC1 USI09 clock (from CMU_TOP)

            - description: CMU_PERIC1 USI10 clock (from CMU_TOP)

            - description: CMU_PERIC1 USI11 clock (from CMU_TOP)

            - description: CMU_PERIC1 USI12 clock (from CMU_TOP)

            - description: CMU_PERIC1 USI13 clock (from CMU_TOP)



        clock-names:

          items:

            - const: oscclk

            - const: bus

            - const: speedy

            - const: cam0

            - const: cam1

            - const: uart

            - const: usi4

            - const: usi5

            - const: usi6

            - const: usi7

            - const: usi8

            - const: usi9

            - const: usi10

            - const: usi11

            - const: usi12

            - const: usi13



  - if:

      properties:

        compatible:

          contains:

            const: samsung,exynos8895-cmu-peris



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (26 MHz)

            - description: CMU_PERIS BUS clock (from CMU_TOP)



        clock-names:

          items:

            - const: oscclk

            - const: bus



  - if:

      properties:

        compatible:

          contains:

            const: samsung,exynos8895-cmu-top



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (26 MHz)



        clock-names:

          items:

            - const: oscclk



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/samsung,exynos8895.h>



    cmu_fsys1: clock-controller@11400000 {

        compatible = "samsung,exynos8895-cmu-fsys1";

        reg = <0x11400000 0x8000>;

        #clock-cells = <1>;



        clocks = <&oscclk>,

                 <&cmu_top CLK_DOUT_CMU_FSYS1_BUS>,

                 <&cmu_top CLK_DOUT_CMU_FSYS1_PCIE>,

                 <&cmu_top CLK_DOUT_CMU_FSYS1_UFS_CARD>,

                 <&cmu_top CLK_DOUT_CMU_FSYS1_MMC_CARD>;

        clock-names = "oscclk", "bus", "pcie", "ufs", "mmc";

    };



...

drivers/clk/samsung/Makefile

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@@ -20,6 +20,7 @@ obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos-arm64.o 
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)	+= clk-exynos7.o

obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)	+= clk-exynos7885.o

obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)	+= clk-exynos850.o

obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)	+= clk-exynos8895.o

obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)	+= clk-exynosautov9.o

obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)	+= clk-exynosautov920.o

obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK)	+= clk-gs101.o

drivers/clk/samsung/clk-exynos8895.c

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File added.

Preview size limit exceeded, changes collapsed.

drivers/clk/samsung/clk-exynosautov920.c

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@@ -19,6 +19,10 @@ 
/* NOTE: Must be equal to the last clock ID increased by one */

#define CLKS_NR_TOP			(DOUT_CLKCMU_TAA_NOC + 1)

#define CLKS_NR_PERIC0			(CLK_DOUT_PERIC0_I3C + 1)

#define CLKS_NR_PERIC1			(CLK_DOUT_PERIC1_I3C + 1)

#define CLKS_NR_MISC			(CLK_DOUT_MISC_OSC_DIV2 + 1)

#define CLKS_NR_HSI0			(CLK_DOUT_HSI0_PCIE_APB + 1)

#define CLKS_NR_HSI1			(CLK_MOUT_HSI1_USBDRD + 1)



/* ---- CMU_TOP ------------------------------------------------------------ */
@@ -974,6 +978,8 @@ static const struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initcon 
		"mout_shared5_pll", 1, 3, 0),

	FFACTOR(DOUT_SHARED5_DIV4, "dout_shared5_div4",

		"mout_shared5_pll", 1, 4, 0),

	FFACTOR(DOUT_TCXO_DIV2, "dout_tcxo_div2",

		"oscclk", 1, 2, 0),

};



static const struct samsung_cmu_info top_cmu_info __initconst = {
@@ -1139,6 +1145,277 @@ static const struct samsung_cmu_info peric0_cmu_info __initconst = { 
	.clk_name		= "noc",

};



/* ---- CMU_PERIC1 --------------------------------------------------------- */



/* Register Offset definitions for CMU_PERIC1 (0x10C00000) */

#define PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER	0x600

#define PLL_CON0_MUX_CLKCMU_PERIC1_NOC_USER	0x610

#define CLK_CON_MUX_MUX_CLK_PERIC1_I3C		0x1000

#define CLK_CON_MUX_MUX_CLK_PERIC1_USI09_USI	0x1004

#define CLK_CON_MUX_MUX_CLK_PERIC1_USI10_USI	0x1008

#define CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI	0x100c

#define CLK_CON_MUX_MUX_CLK_PERIC1_USI12_USI	0x1010

#define CLK_CON_MUX_MUX_CLK_PERIC1_USI13_USI	0x1014

#define CLK_CON_MUX_MUX_CLK_PERIC1_USI14_USI	0x1018

#define CLK_CON_MUX_MUX_CLK_PERIC1_USI15_USI	0x101c

#define CLK_CON_MUX_MUX_CLK_PERIC1_USI16_USI	0x1020

#define CLK_CON_MUX_MUX_CLK_PERIC1_USI17_USI	0x1024

#define CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C	0x1028

#define CLK_CON_DIV_DIV_CLK_PERIC1_I3C		0x1800

#define CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI	0x1804

#define CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI	0x1808

#define CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI	0x180c

#define CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI	0x1810

#define CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI	0x1814

#define CLK_CON_DIV_DIV_CLK_PERIC1_USI14_USI	0x1818

#define CLK_CON_DIV_DIV_CLK_PERIC1_USI15_USI	0x181c

#define CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI	0x1820

#define CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI	0x1824

#define CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C	0x1828



static const unsigned long peric1_clk_regs[] __initconst = {

	PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER,

	PLL_CON0_MUX_CLKCMU_PERIC1_NOC_USER,

	CLK_CON_MUX_MUX_CLK_PERIC1_I3C,

	CLK_CON_MUX_MUX_CLK_PERIC1_USI09_USI,

	CLK_CON_MUX_MUX_CLK_PERIC1_USI10_USI,

	CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI,

	CLK_CON_MUX_MUX_CLK_PERIC1_USI12_USI,

	CLK_CON_MUX_MUX_CLK_PERIC1_USI13_USI,

	CLK_CON_MUX_MUX_CLK_PERIC1_USI14_USI,

	CLK_CON_MUX_MUX_CLK_PERIC1_USI15_USI,

	CLK_CON_MUX_MUX_CLK_PERIC1_USI16_USI,

	CLK_CON_MUX_MUX_CLK_PERIC1_USI17_USI,

	CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C,

	CLK_CON_DIV_DIV_CLK_PERIC1_I3C,

	CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI,

	CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI,

	CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI,

	CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI,

	CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI,

	CLK_CON_DIV_DIV_CLK_PERIC1_USI14_USI,

	CLK_CON_DIV_DIV_CLK_PERIC1_USI15_USI,

	CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI,

	CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI,

	CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C,

};



/* List of parent clocks for Muxes in CMU_PERIC1 */

PNAME(mout_peric1_ip_user_p) = { "oscclk", "dout_clkcmu_peric1_ip" };

PNAME(mout_peric1_noc_user_p) = { "oscclk", "dout_clkcmu_peric1_noc" };

PNAME(mout_peric1_usi_p) = { "oscclk", "mout_peric1_ip_user" };



static const struct samsung_mux_clock peric1_mux_clks[] __initconst = {

	MUX(CLK_MOUT_PERIC1_IP_USER, "mout_peric1_ip_user",

	    mout_peric1_ip_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_IP_USER, 4, 1),

	MUX(CLK_MOUT_PERIC1_NOC_USER, "mout_peric1_noc_user",

	    mout_peric1_noc_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_NOC_USER, 4, 1),

	/* USI09 ~ USI17 */

	MUX(CLK_MOUT_PERIC1_USI09_USI, "mout_peric1_usi09_usi",

	    mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI09_USI, 0, 1),

	MUX(CLK_MOUT_PERIC1_USI10_USI, "mout_peric1_usi10_usi",

	    mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI10_USI, 0, 1),

	MUX(CLK_MOUT_PERIC1_USI11_USI, "mout_peric1_usi11_usi",

	    mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI11_USI, 0, 1),

	MUX(CLK_MOUT_PERIC1_USI12_USI, "mout_peric1_usi12_usi",

	    mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI12_USI, 0, 1),

	MUX(CLK_MOUT_PERIC1_USI13_USI, "mout_peric1_usi13_usi",

	    mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI13_USI, 0, 1),

	MUX(CLK_MOUT_PERIC1_USI14_USI, "mout_peric1_usi14_usi",

	    mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI14_USI, 0, 1),

	MUX(CLK_MOUT_PERIC1_USI15_USI, "mout_peric1_usi15_usi",

	    mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI15_USI, 0, 1),

	MUX(CLK_MOUT_PERIC1_USI16_USI, "mout_peric1_usi16_usi",

	    mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI16_USI, 0, 1),

	MUX(CLK_MOUT_PERIC1_USI17_USI, "mout_peric1_usi17_usi",

	    mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI17_USI, 0, 1),

	/* USI_I2C */

	MUX(CLK_MOUT_PERIC1_USI_I2C, "mout_peric1_usi_i2c",

	    mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_USI_I2C, 0, 1),

	/* USI_I3C */

	MUX(CLK_MOUT_PERIC1_I3C, "mout_peric1_i3c",

	    mout_peric1_usi_p, CLK_CON_MUX_MUX_CLK_PERIC1_I3C, 0, 1),

};



static const struct samsung_div_clock peric1_div_clks[] __initconst = {

	/* USI09 ~ USI17 */

	DIV(CLK_DOUT_PERIC1_USI09_USI, "dout_peric1_usi09_usi",

	    "mout_peric1_usi09_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI09_USI,

	    0, 4),

	DIV(CLK_DOUT_PERIC1_USI10_USI, "dout_peric1_usi10_usi",

	    "mout_peric1_usi10_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI,

	    0, 4),

	DIV(CLK_DOUT_PERIC1_USI11_USI, "dout_peric1_usi11_usi",

	    "mout_peric1_usi11_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI,

	    0, 4),

	DIV(CLK_DOUT_PERIC1_USI12_USI, "dout_peric1_usi12_usi",

	    "mout_peric1_usi12_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI,

	    0, 4),

	DIV(CLK_DOUT_PERIC1_USI13_USI, "dout_peric1_usi13_usi",

	    "mout_peric1_usi13_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI,

	    0, 4),

	DIV(CLK_DOUT_PERIC1_USI14_USI, "dout_peric1_usi14_usi",

	    "mout_peric1_usi14_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI14_USI,

	    0, 4),

	DIV(CLK_DOUT_PERIC1_USI15_USI, "dout_peric1_usi15_usi",

	    "mout_peric1_usi15_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI15_USI,

	    0, 4),

	DIV(CLK_DOUT_PERIC1_USI16_USI, "dout_peric1_usi16_usi",

	    "mout_peric1_usi16_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI16_USI,

	    0, 4),

	DIV(CLK_DOUT_PERIC1_USI17_USI, "dout_peric1_usi17_usi",

	    "mout_peric1_usi17_usi", CLK_CON_DIV_DIV_CLK_PERIC1_USI17_USI,

	    0, 4),

	/* USI_I2C */

	DIV(CLK_DOUT_PERIC1_USI_I2C, "dout_peric1_usi_i2c",

	    "mout_peric1_usi_i2c", CLK_CON_DIV_DIV_CLK_PERIC1_USI_I2C, 0, 4),

	/* USI_I3C */

	DIV(CLK_DOUT_PERIC1_I3C, "dout_peric1_i3c",

	    "mout_peric1_i3c", CLK_CON_DIV_DIV_CLK_PERIC1_I3C, 0, 4),

};



static const struct samsung_cmu_info peric1_cmu_info __initconst = {

	.mux_clks		= peric1_mux_clks,

	.nr_mux_clks		= ARRAY_SIZE(peric1_mux_clks),

	.div_clks		= peric1_div_clks,

	.nr_div_clks		= ARRAY_SIZE(peric1_div_clks),

	.nr_clk_ids		= CLKS_NR_PERIC1,

	.clk_regs		= peric1_clk_regs,

	.nr_clk_regs		= ARRAY_SIZE(peric1_clk_regs),

	.clk_name		= "noc",

};



/* ---- CMU_MISC --------------------------------------------------------- */



/* Register Offset definitions for CMU_MISC (0x10020000) */

#define PLL_CON0_MUX_CLKCMU_MISC_NOC_USER	0x600

#define CLK_CON_MUX_MUX_CLK_MISC_GIC		0x1000

#define CLK_CON_DIV_CLKCMU_OTP			0x1800

#define CLK_CON_DIV_DIV_CLK_MISC_NOCP		0x1804

#define CLK_CON_DIV_DIV_CLK_MISC_OSC_DIV2	0x1808



static const unsigned long misc_clk_regs[] __initconst = {

	PLL_CON0_MUX_CLKCMU_MISC_NOC_USER,

	CLK_CON_MUX_MUX_CLK_MISC_GIC,

	CLK_CON_DIV_CLKCMU_OTP,

	CLK_CON_DIV_DIV_CLK_MISC_NOCP,

	CLK_CON_DIV_DIV_CLK_MISC_OSC_DIV2,

};



/* List of parent clocks for Muxes in CMU_MISC */

PNAME(mout_misc_noc_user_p) = { "oscclk", "dout_clkcmu_misc_noc" };

PNAME(mout_misc_gic_p) = { "dout_misc_nocp", "oscclk" };



static const struct samsung_mux_clock misc_mux_clks[] __initconst = {

	MUX(CLK_MOUT_MISC_NOC_USER, "mout_misc_noc_user",

	    mout_misc_noc_user_p, PLL_CON0_MUX_CLKCMU_MISC_NOC_USER, 4, 1),

	MUX(CLK_MOUT_MISC_GIC, "mout_misc_gic",

	    mout_misc_gic_p, CLK_CON_MUX_MUX_CLK_MISC_GIC, 0, 1),

};



static const struct samsung_div_clock misc_div_clks[] __initconst = {

	DIV(CLK_DOUT_MISC_NOCP, "dout_misc_nocp",

	    "mout_misc_noc_user", CLK_CON_DIV_DIV_CLK_MISC_NOCP,

	    0, 3),

};



static const struct samsung_fixed_factor_clock misc_fixed_factor_clks[] __initconst = {

	FFACTOR(CLK_DOUT_MISC_OTP, "dout_misc_otp",

		"oscclk", 1, 10, 0),

	FFACTOR(CLK_DOUT_MISC_OSC_DIV2, "dout_misc_osc_div2",

		"oscclk", 1, 2, 0),

};



static const struct samsung_cmu_info misc_cmu_info __initconst = {

	.mux_clks		= misc_mux_clks,

	.nr_mux_clks		= ARRAY_SIZE(misc_mux_clks),

	.div_clks		= misc_div_clks,

	.nr_div_clks		= ARRAY_SIZE(misc_div_clks),

	.fixed_factor_clks	= misc_fixed_factor_clks,

	.nr_fixed_factor_clks	= ARRAY_SIZE(misc_fixed_factor_clks),

	.nr_clk_ids		= CLKS_NR_MISC,

	.clk_regs		= misc_clk_regs,

	.nr_clk_regs		= ARRAY_SIZE(misc_clk_regs),

	.clk_name		= "noc",

};



/* ---- CMU_HSI0 --------------------------------------------------------- */



/* Register Offset definitions for CMU_HSI0 (0x16000000) */

#define PLL_CON0_MUX_CLKCMU_HSI0_NOC_USER	0x600

#define CLK_CON_DIV_DIV_CLK_HSI0_PCIE_APB	0x1800



static const unsigned long hsi0_clk_regs[] __initconst = {

	PLL_CON0_MUX_CLKCMU_HSI0_NOC_USER,

	CLK_CON_DIV_DIV_CLK_HSI0_PCIE_APB,

};



/* List of parent clocks for Muxes in CMU_HSI0 */

PNAME(mout_hsi0_noc_user_p) = { "oscclk", "dout_clkcmu_hsi0_noc" };



static const struct samsung_mux_clock hsi0_mux_clks[] __initconst = {

	MUX(CLK_MOUT_HSI0_NOC_USER, "mout_hsi0_noc_user",

	    mout_hsi0_noc_user_p, PLL_CON0_MUX_CLKCMU_HSI0_NOC_USER, 4, 1),

};



static const struct samsung_div_clock hsi0_div_clks[] __initconst = {

	DIV(CLK_DOUT_HSI0_PCIE_APB, "dout_hsi0_pcie_apb",

	    "mout_hsi0_noc_user", CLK_CON_DIV_DIV_CLK_HSI0_PCIE_APB,

	    0, 4),

};



static const struct samsung_cmu_info hsi0_cmu_info __initconst = {

	.mux_clks		= hsi0_mux_clks,

	.nr_mux_clks		= ARRAY_SIZE(hsi0_mux_clks),

	.div_clks		= hsi0_div_clks,

	.nr_div_clks		= ARRAY_SIZE(hsi0_div_clks),

	.nr_clk_ids		= CLKS_NR_HSI0,

	.clk_regs		= hsi0_clk_regs,

	.nr_clk_regs		= ARRAY_SIZE(hsi0_clk_regs),

	.clk_name		= "noc",

};



/* ---- CMU_HSI1 --------------------------------------------------------- */



/* Register Offset definitions for CMU_HSI1 (0x16400000) */

#define PLL_CON0_MUX_CLKCMU_HSI1_MMC_CARD_USER	0x600

#define PLL_CON0_MUX_CLKCMU_HSI1_NOC_USER	0x610

#define PLL_CON0_MUX_CLKCMU_HSI1_USBDRD_USER	0x620

#define CLK_CON_MUX_MUX_CLK_HSI1_USBDRD		0x1000



static const unsigned long hsi1_clk_regs[] __initconst = {

	PLL_CON0_MUX_CLKCMU_HSI1_MMC_CARD_USER,

	PLL_CON0_MUX_CLKCMU_HSI1_NOC_USER,

	PLL_CON0_MUX_CLKCMU_HSI1_USBDRD_USER,

	CLK_CON_MUX_MUX_CLK_HSI1_USBDRD,

};



/* List of parent clocks for Muxes in CMU_HSI1 */

PNAME(mout_hsi1_mmc_card_user_p) = {"oscclk", "dout_clkcmu_hsi1_mmc_card"};

PNAME(mout_hsi1_noc_user_p) = { "oscclk", "dout_clkcmu_hsi1_noc" };

PNAME(mout_hsi1_usbdrd_user_p) = { "oscclk", "mout_clkcmu_hsi1_usbdrd" };

PNAME(mout_hsi1_usbdrd_p) = { "dout_tcxo_div2", "mout_hsi1_usbdrd_user" };



static const struct samsung_mux_clock hsi1_mux_clks[] __initconst = {

	MUX(CLK_MOUT_HSI1_MMC_CARD_USER, "mout_hsi1_mmc_card_user",

	    mout_hsi1_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_HSI1_MMC_CARD_USER, 4, 1),

	MUX(CLK_MOUT_HSI1_NOC_USER, "mout_hsi1_noc_user",

	    mout_hsi1_noc_user_p, PLL_CON0_MUX_CLKCMU_HSI1_NOC_USER, 4, 1),

	MUX(CLK_MOUT_HSI1_USBDRD_USER, "mout_hsi1_usbdrd_user",

	    mout_hsi1_usbdrd_user_p, PLL_CON0_MUX_CLKCMU_HSI1_USBDRD_USER, 4, 1),

	MUX(CLK_MOUT_HSI1_USBDRD, "mout_hsi1_usbdrd",

	    mout_hsi1_usbdrd_p, CLK_CON_MUX_MUX_CLK_HSI1_USBDRD, 4, 1),

};



static const struct samsung_cmu_info hsi1_cmu_info __initconst = {

	.mux_clks		= hsi1_mux_clks,

	.nr_mux_clks		= ARRAY_SIZE(hsi1_mux_clks),

	.nr_clk_ids		= CLKS_NR_HSI1,

	.clk_regs		= hsi1_clk_regs,

	.nr_clk_regs		= ARRAY_SIZE(hsi1_clk_regs),

	.clk_name		= "noc",

};



static int __init exynosautov920_cmu_probe(struct platform_device *pdev)

{

	const struct samsung_cmu_info *info;
@@ -1154,7 +1431,20 @@ static const struct of_device_id exynosautov920_cmu_of_match[] = { 
	{

		.compatible = "samsung,exynosautov920-cmu-peric0",

		.data = &peric0_cmu_info,

	}, {

		 .compatible = "samsung,exynosautov920-cmu-peric1",

		 .data = &peric1_cmu_info,

	}, {

		 .compatible = "samsung,exynosautov920-cmu-misc",

		 .data = &misc_cmu_info,

	}, {

		.compatible = "samsung,exynosautov920-cmu-hsi0",

		.data = &hsi0_cmu_info,

	}, {

		.compatible = "samsung,exynosautov920-cmu-hsi1",

		.data = &hsi1_cmu_info,

	},

	{ }

};



static struct platform_driver exynosautov920_cmu_driver __refdata = {

drivers/clk/samsung/clk-fsd.c

+16 −7
Original line number Diff line number Diff line
@@ -82,6 +82,15 @@ 
#define GAT_CMU_NS_BRDG_CMU_IPCLKPORT_CLK__PSOC_CMU__CLK_CMU	0x205c

#define GAT_CMU_SYSREG_CMU_IPCLKPORT_PCLK		0x2060



/* NOTE: Must be equal to the last clock ID increased by one */

#define CLKS_NR_CMU		(GAT_CMU_FSYS0_SHARED0DIV4 + 1)

#define CLKS_NR_PERIC		(PERIC_DOUT_RGMII_CLK + 1)

#define CLKS_NR_FSYS0		(FSYS0_DOUT_FSYS0_PERIBUS_GRP + 1)

#define CLKS_NR_FSYS1		(PCIE_LINK1_IPCLKPORT_SLV_ACLK + 1)

#define CLKS_NR_IMEM		(IMEM_TMU_GT_IPCLKPORT_I_CLK_TS + 1)

#define CLKS_NR_MFC		(MFC_MFC_IPCLKPORT_ACLK + 1)

#define CLKS_NR_CAM_CSI		(CAM_CSI2_3_IPCLKPORT_I_ACLK + 1)



static const unsigned long cmu_clk_regs[] __initconst = {

	PLL_LOCKTIME_PLL_SHARED0,

	PLL_LOCKTIME_PLL_SHARED1,
@@ -300,7 +309,7 @@ static const struct samsung_cmu_info cmu_cmu_info __initconst = { 
	.nr_div_clks		= ARRAY_SIZE(cmu_div_clks),

	.gate_clks		= cmu_gate_clks,

	.nr_gate_clks		= ARRAY_SIZE(cmu_gate_clks),

	.nr_clk_ids		= CMU_NR_CLK,

	.nr_clk_ids		= CLKS_NR_CMU,

	.clk_regs		= cmu_clk_regs,

	.nr_clk_regs		= ARRAY_SIZE(cmu_clk_regs),

};
@@ -665,7 +674,7 @@ static const struct samsung_cmu_info peric_cmu_info __initconst = { 
	.nr_gate_clks		= ARRAY_SIZE(peric_gate_clks),

	.fixed_clks		= peric_fixed_clks,

	.nr_fixed_clks		= ARRAY_SIZE(peric_fixed_clks),

	.nr_clk_ids		= PERIC_NR_CLK,

	.nr_clk_ids		= CLKS_NR_PERIC,

	.clk_regs		= peric_clk_regs,

	.nr_clk_regs		= ARRAY_SIZE(peric_clk_regs),

	.clk_name		= "dout_cmu_pll_shared0_div4",
@@ -964,7 +973,7 @@ static const struct samsung_cmu_info fsys0_cmu_info __initconst = { 
	.nr_gate_clks		= ARRAY_SIZE(fsys0_gate_clks),

	.fixed_clks		= fsys0_fixed_clks,

	.nr_fixed_clks		= ARRAY_SIZE(fsys0_fixed_clks),

	.nr_clk_ids		= FSYS0_NR_CLK,

	.nr_clk_ids		= CLKS_NR_FSYS0,

	.clk_regs		= fsys0_clk_regs,

	.nr_clk_regs		= ARRAY_SIZE(fsys0_clk_regs),

	.clk_name		= "dout_cmu_fsys0_shared1div4",
@@ -1136,7 +1145,7 @@ static const struct samsung_cmu_info fsys1_cmu_info __initconst = { 
	.nr_gate_clks		= ARRAY_SIZE(fsys1_gate_clks),

	.fixed_clks		= fsys1_fixed_clks,

	.nr_fixed_clks		= ARRAY_SIZE(fsys1_fixed_clks),

	.nr_clk_ids		= FSYS1_NR_CLK,

	.nr_clk_ids		= CLKS_NR_FSYS1,

	.clk_regs		= fsys1_clk_regs,

	.nr_clk_regs		= ARRAY_SIZE(fsys1_clk_regs),

	.clk_name		= "dout_cmu_fsys1_shared0div4",
@@ -1413,7 +1422,7 @@ static const struct samsung_cmu_info imem_cmu_info __initconst = { 
	.nr_div_clks		= ARRAY_SIZE(imem_div_clks),

	.gate_clks		= imem_gate_clks,

	.nr_gate_clks		= ARRAY_SIZE(imem_gate_clks),

	.nr_clk_ids		= IMEM_NR_CLK,

	.nr_clk_ids		= CLKS_NR_IMEM,

	.clk_regs		= imem_clk_regs,

	.nr_clk_regs		= ARRAY_SIZE(imem_clk_regs),

};
@@ -1538,7 +1547,7 @@ static const struct samsung_cmu_info mfc_cmu_info __initconst = { 
	.nr_div_clks		= ARRAY_SIZE(mfc_div_clks),

	.gate_clks		= mfc_gate_clks,

	.nr_gate_clks		= ARRAY_SIZE(mfc_gate_clks),

	.nr_clk_ids		= MFC_NR_CLK,

	.nr_clk_ids		= CLKS_NR_MFC,

	.clk_regs		= mfc_clk_regs,

	.nr_clk_regs		= ARRAY_SIZE(mfc_clk_regs),

};
@@ -1742,7 +1751,7 @@ static const struct samsung_cmu_info cam_csi_cmu_info __initconst = { 
	.nr_div_clks		= ARRAY_SIZE(cam_csi_div_clks),

	.gate_clks		= cam_csi_gate_clks,

	.nr_gate_clks		= ARRAY_SIZE(cam_csi_gate_clks),

	.nr_clk_ids		= CAM_CSI_NR_CLK,

	.nr_clk_ids		= CLKS_NR_CAM_CSI,

	.clk_regs		= cam_csi_clk_regs,

	.nr_clk_regs		= ARRAY_SIZE(cam_csi_clk_regs),

};