Commit 31848987 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'soc-newsoc-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc 

Pull sophgo SoC devicetree updates from Arnd Bergmann:
 "The Sophgo SG2044 SoC is their second generation server chip with 64
  cores, following the SG2042.

  In addition, there are minor updates for the cv180x SoCs"

* tag 'soc-newsoc-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
  riscv: dts: sophgo: switch precise compatible for existed clock device for CV18XX
  riscv: dts: sophgo: Add initial device tree of Sophgo SRD3-10
  dt-bindings: riscv: sophgo: Add SG2044 compatible string
  dt-bindings: interrupt-controller: Add Sophgo SG2044 PLIC
  dt-bindings: interrupt-controller: Add Sophgo SG2044 CLINT mswi
  riscv: dts: sopgho: use SOC_PERIPHERAL_IRQ to calculate interrupt number
  riscv: dts: sophgo: rename header file cv18xx.dtsi to cv180x.dtsi
  riscv: dts: sophgo: Move riscv cpu definition to a separate file
  riscv: dts: sophgo: Move all soc specific device into soc dtsi file
  riscv: sophgo: dts: Add spi controller for SG2042
  riscv: dts: sophgo: sg2042: add pinctrl support
parents ec71f661 9bba6186

Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml

+1 −0
Original line number Diff line number Diff line
@@ -70,6 +70,7 @@ properties: 
              - sophgo,cv1812h-plic

              - sophgo,sg2002-plic

              - sophgo,sg2042-plic

              - sophgo,sg2044-plic

              - thead,th1520-plic

          - const: thead,c900-plic

      - items:

Documentation/devicetree/bindings/interrupt-controller/thead,c900-aclint-mswi.yaml

+1 −0
Original line number Diff line number Diff line
@@ -14,6 +14,7 @@ properties: 
    items:

      - enum:

          - sophgo,sg2042-aclint-mswi

          - sophgo,sg2044-aclint-mswi

      - const: thead,c900-aclint-mswi



  reg:

Documentation/devicetree/bindings/riscv/sophgo.yaml

+4 −0
Original line number Diff line number Diff line
@@ -35,6 +35,10 @@ properties: 
          - enum:

              - milkv,pioneer

          - const: sophgo,sg2042

      - items:

          - enum:

              - sophgo,srd3-10

          - const: sophgo,sg2044



additionalProperties: true

arch/riscv/boot/dts/sophgo/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -3,3 +3,4 @@ dtb-$(CONFIG_ARCH_SOPHGO) += cv1800b-milkv-duo.dtb 
dtb-$(CONFIG_ARCH_SOPHGO) += cv1812h-huashan-pi.dtb

dtb-$(CONFIG_ARCH_SOPHGO) += sg2002-licheerv-nano-b.dtb

dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-milkv-pioneer.dtb

dtb-$(CONFIG_ARCH_SOPHGO) += sg2044-sophgo-srd3-10.dtb

arch/riscv/boot/dts/sophgo/cv1800b.dtsi

+28 −11
Original line number Diff line number Diff line
@@ -3,8 +3,11 @@ 
 * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>

 */



#define SOC_PERIPHERAL_IRQ(nr)	((nr) + 16)



#include <dt-bindings/pinctrl/pinctrl-cv1800b.h>

#include "cv18xx.dtsi"

#include "cv180x-cpus.dtsi"

#include "cv180x.dtsi"



/ {

	compatible = "sophgo,cv1800b";
@@ -15,23 +18,37 @@ memory@80000000 { 
	};



	soc {

		interrupt-parent = <&plic>;

		dma-noncoherent;



		pinctrl: pinctrl@3001000 {

			compatible = "sophgo,cv1800b-pinctrl";

			reg = <0x03001000 0x1000>,

			      <0x05027000 0x1000>;

			reg-names = "sys", "rtc";

		};

	};



		clk: clock-controller@3002000 {

			compatible = "sophgo,cv1800b-clk";

			reg = <0x03002000 0x1000>;

			clocks = <&osc>;

			#clock-cells = <1>;

		};



&plic {

		plic: interrupt-controller@70000000 {

			compatible = "sophgo,cv1800b-plic", "thead,c900-plic";

			reg = <0x70000000 0x4000000>;

			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;

			interrupt-controller;

			#address-cells = <0>;

			#interrupt-cells = <2>;

			riscv,ndev = <101>;

		};



&clint {

		clint: timer@74000000 {

			compatible = "sophgo,cv1800b-clint", "thead,c900-clint";

			reg = <0x74000000 0x10000>;

			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;

		};

	};



&clk {

	compatible = "sophgo,cv1800-clk";

};