Commit 31ba2993 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'renesas-clk-for-v6.13-tag1' of... 

Merge tag 'renesas-clk-for-v6.13-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas

Pull Renesas clk driver updates from Geert Uytterhoeven:

 - Add Cortex-A55 core clocks and Interrupt Control Unit (ICU) clock
   and reset on Renesas RZ/V2H(P)

* tag 'renesas-clk-for-v6.13-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: r8a779h0: Drop CLK_PLL2_DIV2 to clarify ZCn clocks
  clk: renesas: r9a09g057: Add clock and reset entries for ICU
  clk: renesas: r9a09g057: Add CA55 core clocks
  clk: renesas: Remove duplicate and trailing empty lines
parents 9852d85e 92850bed

drivers/clk/renesas/clk-r8a73a4.c

+0 −1
Original line number Diff line number Diff line
@@ -64,7 +64,6 @@ r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg, 
	unsigned int mult = 1;

	unsigned int div = 1;





	if (!strcmp(name, "main")) {

		u32 ckscr = readl(base + CPG_CKSCR);

drivers/clk/renesas/clk-r8a7778.c

+0 −1
Original line number Diff line number Diff line
@@ -67,7 +67,6 @@ r8a7778_cpg_register_clock(struct device_node *np, const char *name) 
	return ERR_PTR(-EINVAL);

}





static void __init r8a7778_cpg_clocks_init(struct device_node *np)

{

	struct clk_onecell_data *data;

drivers/clk/renesas/r8a779a0-cpg-mssr.c

+0 −1
Original line number Diff line number Diff line
@@ -266,7 +266,6 @@ static const struct rcar_gen4_cpg_pll_config cpg_pll_configs[4] __initconst = { 
	{ 2,		128,	1,	192,	1,	32,	},

};





static int __init r8a779a0_cpg_mssr_init(struct device *dev)

{

	const struct rcar_gen4_cpg_pll_config *cpg_pll_config;

drivers/clk/renesas/r8a779h0-cpg-mssr.c

+4 −6
Original line number Diff line number Diff line
@@ -37,7 +37,6 @@ enum clk_ids { 
	CLK_PLL5,

	CLK_PLL6,

	CLK_PLL1_DIV2,

	CLK_PLL2_DIV2,

	CLK_PLL3_DIV2,

	CLK_PLL4_DIV2,

	CLK_PLL4_DIV5,
@@ -78,7 +77,6 @@ static const struct cpg_core_clk r8a779h0_core_clks[] __initconst = { 
	DEF_GEN4_PLL_V8_25(".pll6", 6,	CLK_PLL6,		CLK_MAIN),



	DEF_FIXED(".pll1_div2",	CLK_PLL1_DIV2,	CLK_PLL1,	2, 1),

	DEF_FIXED(".pll2_div2",	CLK_PLL2_DIV2,	CLK_PLL2,	2, 1),

	DEF_FIXED(".pll3_div2",	CLK_PLL3_DIV2,	CLK_PLL3,	2, 1),

	DEF_FIXED(".pll4_div2",	CLK_PLL4_DIV2,	CLK_PLL4,	2, 1),

	DEF_FIXED(".pll4_div5",	CLK_PLL4_DIV5,	CLK_PLL4,	5, 1),
@@ -101,10 +99,10 @@ static const struct cpg_core_clk r8a779h0_core_clks[] __initconst = { 
	DEF_RATE(".oco",	CLK_OCO,	32768),



	/* Core Clock Outputs */

	DEF_GEN4_Z("zc0",	R8A779H0_CLK_ZC0,	CLK_TYPE_GEN4_Z,	CLK_PLL2_DIV2,	2, 0),

	DEF_GEN4_Z("zc1",	R8A779H0_CLK_ZC1,	CLK_TYPE_GEN4_Z,	CLK_PLL2_DIV2,	2, 8),

	DEF_GEN4_Z("zc2",	R8A779H0_CLK_ZC2,	CLK_TYPE_GEN4_Z,	CLK_PLL2_DIV2,	2, 32),

	DEF_GEN4_Z("zc3",	R8A779H0_CLK_ZC3,	CLK_TYPE_GEN4_Z,	CLK_PLL2_DIV2,	2, 40),

	DEF_GEN4_Z("zc0",	R8A779H0_CLK_ZC0,	CLK_TYPE_GEN4_Z,	CLK_PLL2,	4, 0),

	DEF_GEN4_Z("zc1",	R8A779H0_CLK_ZC1,	CLK_TYPE_GEN4_Z,	CLK_PLL2,	4, 8),

	DEF_GEN4_Z("zc2",	R8A779H0_CLK_ZC2,	CLK_TYPE_GEN4_Z,	CLK_PLL2,	4, 32),

	DEF_GEN4_Z("zc3",	R8A779H0_CLK_ZC3,	CLK_TYPE_GEN4_Z,	CLK_PLL2,	4, 40),

	DEF_FIXED("s0d2",	R8A779H0_CLK_S0D2,	CLK_S0,		2, 1),

	DEF_FIXED("s0d3",	R8A779H0_CLK_S0D3,	CLK_S0,		3, 1),

	DEF_FIXED("s0d4",	R8A779H0_CLK_S0D4,	CLK_S0,		4, 1),

drivers/clk/renesas/r9a09g011-cpg.c

+0 −1
Original line number Diff line number Diff line
@@ -98,7 +98,6 @@ static const struct clk_div_table dtable_divd[] = { 
	{0, 0},

};





static const struct clk_div_table dtable_divw[] = {

	{0, 6},

	{1, 7},