Commit 31c2bf25 authored by Dmytro Laktyushkin's avatar Dmytro Laktyushkin Committed by Alex Deucher
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drm/amd/display: Fix DPSTREAM CLK on and off sequence 



[Why]
Secondary DP2 display fails to light up in some instances

[How]
Clock needs to be on when DPSTREAMCLK*_EN =1. This change
moves dtbclk_p enable/disable point to make sure this is
the case

Reviewed-by: default avatarCharlene Liu <charlene.liu@amd.com>
Reviewed-by: default avatarDmytro Laktyushkin <dmytro.laktyushkin@amd.com>
Acked-by: default avatarTom Chung <chiahsuan.chung@amd.com>
Signed-off-by: default avatarDaniel Miess <daniel.miess@amd.com>
Signed-off-by: default avatarDmytro Laktyushkin <dmytro.laktyushkin@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent b5abd7f9

drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

+1 −1
Original line number Diff line number Diff line
@@ -1183,9 +1183,9 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx) 
		dto_params.timing = &pipe_ctx->stream->timing;

		dp_hpo_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst;

		if (dccg) {

			dccg->funcs->set_dtbclk_dto(dccg, &dto_params);

			dccg->funcs->disable_symclk32_se(dccg, dp_hpo_inst);

			dccg->funcs->set_dpstreamclk(dccg, REFCLK, tg->inst, dp_hpo_inst);

			dccg->funcs->set_dtbclk_dto(dccg, &dto_params);

		}

	} else if (dccg && dccg->funcs->disable_symclk_se) {

		dccg->funcs->disable_symclk_se(dccg, stream_enc->stream_enc_inst,

drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c

+5 −6
Original line number Diff line number Diff line
@@ -2790,18 +2790,17 @@ void dcn20_enable_stream(struct pipe_ctx *pipe_ctx) 
	}



	if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) {

		dp_hpo_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst;

		dccg->funcs->set_dpstreamclk(dccg, DTBCLK0, tg->inst, dp_hpo_inst);



		phyd32clk = get_phyd32clk_src(link);

		dccg->funcs->enable_symclk32_se(dccg, dp_hpo_inst, phyd32clk);



		dto_params.otg_inst = tg->inst;

		dto_params.pixclk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10;

		dto_params.num_odm_segments = get_odm_segment_count(pipe_ctx);

		dto_params.timing = &pipe_ctx->stream->timing;

		dto_params.ref_dtbclk_khz = dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(dc->clk_mgr);

		dccg->funcs->set_dtbclk_dto(dccg, &dto_params);

		dp_hpo_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst;

		dccg->funcs->set_dpstreamclk(dccg, DTBCLK0, tg->inst, dp_hpo_inst);



		phyd32clk = get_phyd32clk_src(link);

		dccg->funcs->enable_symclk32_se(dccg, dp_hpo_inst, phyd32clk);

	} else {

		if (dccg->funcs->enable_symclk_se)

			dccg->funcs->enable_symclk_se(dccg, stream_enc->stream_enc_inst,