Commit 3227c3a8 authored by Sascha Bischoff's avatar Sascha Bischoff Committed by Marc Zyngier
Browse files

irqchip/gic-v5: Check if impl is virt capable 



Now that there is support for creating a GICv5-based guest with KVM,
check that the hardware itself supports virtualisation, skipping the
setting of struct gic_kvm_info if not.

Note: If native GICv5 virt is not supported, then nor is
FEAT_GCIE_LEGACY, so we are able to skip altogether.

Signed-off-by: default avatarSascha Bischoff <sascha.bischoff@arm.com>
Reviewed-by: default avatarLorenzo Pieralisi <lpieralisi@kernel.org>
Reviewed-by: default avatarJonathan Cameron <jonathan.cameron@huawei.com>
Link: https://patch.msgid.link/20260128175919.3828384-33-sascha.bischoff@arm.com


[maz: cosmetic changes]
Signed-off-by: default avatarMarc Zyngier <maz@kernel.org>
parent 9435c1e1

drivers/irqchip/irq-gic-v5-irs.c

+2 −0
Original line number Diff line number Diff line
@@ -743,6 +743,8 @@ static int __init gicv5_irs_init(struct device_node *node) 
	 * be consistent across IRSes by the architecture.

	 */

	if (list_empty(&irs_nodes)) {

		idr = irs_readl_relaxed(irs_data, GICV5_IRS_IDR0);

		gicv5_global_data.virt_capable = !FIELD_GET(GICV5_IRS_IDR0_VIRT, idr);



		idr = irs_readl_relaxed(irs_data, GICV5_IRS_IDR1);

		irs_setup_pri_bits(idr);

drivers/irqchip/irq-gic-v5.c

+10 −0
Original line number Diff line number Diff line
@@ -1064,6 +1064,16 @@ static struct gic_kvm_info gic_v5_kvm_info __initdata; 


static void __init gic_of_setup_kvm_info(struct device_node *node)

{

	/*

	 * If we don't have native GICv5 virtualisation support, then

	 * we also don't have FEAT_GCIE_LEGACY - the architecture

	 * forbids this combination.

	 */

	if (!gicv5_global_data.virt_capable) {

		pr_info("GIC implementation is not virtualization capable\n");

		return;

	}



	gic_v5_kvm_info.type = GIC_V5;



	/* GIC Virtual CPU interface maintenance interrupt */

include/linux/irqchip/arm-gic-v5.h

+4 −0
Original line number Diff line number Diff line
@@ -43,6 +43,7 @@ 
/*

 * IRS registers and tables structures

 */

#define GICV5_IRS_IDR0			0x0000

#define GICV5_IRS_IDR1			0x0004

#define GICV5_IRS_IDR2			0x0008

#define GICV5_IRS_IDR5			0x0014
@@ -63,6 +64,8 @@ 
#define GICV5_IRS_IST_STATUSR		0x0194

#define GICV5_IRS_MAP_L2_ISTR		0x01c0



#define GICV5_IRS_IDR0_VIRT		BIT(6)



#define GICV5_IRS_IDR1_PRIORITY_BITS	GENMASK(22, 20)

#define GICV5_IRS_IDR1_IAFFID_BITS	GENMASK(19, 16)
@@ -278,6 +281,7 @@ struct gicv5_chip_data { 
	u8			cpuif_pri_bits;

	u8			cpuif_id_bits;

	u8			irs_pri_bits;

	bool			virt_capable;

	struct {

		__le64 *l1ist_addr;

		u32 l2_size;