Commit 3239c52f authored by Hui Min Mina Chou's avatar Hui Min Mina Chou Committed by Anup Patel
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RISC-V: KVM: Flush VS-stage TLB after VCPU migration for Andes cores 



Most implementations cache the combined result of two-stage translation,
but some, like Andes cores, use split TLBs that store VS-stage and
G-stage entries separately.

On such systems, when a VCPU migrates to another CPU, an additional
HFENCE.VVMA is required to avoid using stale VS-stage entries, which
could otherwise cause guest faults.

Introduce a static key to identify CPUs with split two-stage TLBs.
When enabled, KVM issues an extra HFENCE.VVMA on VCPU migration to
prevent stale VS-stage mappings.

Signed-off-by: default avatarHui Min Mina Chou <minachou@andestech.com>
Signed-off-by: default avatarBen Zong-You Xie <ben717@andestech.com>
Reviewed-by: default avatarRadim Krčmář <rkrcmar@ventanamicro.com>
Reviewed-by: default avatarNutty Liu <nutty.liu@hotmail.com>
Link: https://lore.kernel.org/r/20251117084555.157642-1-minachou@andestech.com


Signed-off-by: default avatarAnup Patel <anup@brainfault.org>
parent 974555d6

arch/riscv/include/asm/kvm_host.h

+3 −0
Original line number Diff line number Diff line
@@ -330,4 +330,7 @@ bool kvm_riscv_vcpu_stopped(struct kvm_vcpu *vcpu); 


void kvm_riscv_vcpu_record_steal_time(struct kvm_vcpu *vcpu);



/* Flags representing implementation specific details */

DECLARE_STATIC_KEY_FALSE(kvm_riscv_vsstage_tlb_no_gpa);



#endif /* __RISCV_KVM_HOST_H__ */

arch/riscv/include/asm/kvm_tlb.h

+1 −0
Original line number Diff line number Diff line
@@ -49,6 +49,7 @@ void kvm_riscv_local_hfence_vvma_gva(unsigned long vmid, 
				     unsigned long gva, unsigned long gvsz,

				     unsigned long order);

void kvm_riscv_local_hfence_vvma_all(unsigned long vmid);

void kvm_riscv_local_tlb_sanitize(struct kvm_vcpu *vcpu);



void kvm_riscv_tlb_flush_process(struct kvm_vcpu *vcpu);

arch/riscv/include/asm/kvm_vmid.h

+0 −1
Original line number Diff line number Diff line
@@ -22,6 +22,5 @@ unsigned long kvm_riscv_gstage_vmid_bits(void); 
int kvm_riscv_gstage_vmid_init(struct kvm *kvm);

bool kvm_riscv_gstage_vmid_ver_changed(struct kvm_vmid *vmid);

void kvm_riscv_gstage_vmid_update(struct kvm_vcpu *vcpu);

void kvm_riscv_gstage_vmid_sanitize(struct kvm_vcpu *vcpu);



#endif

arch/riscv/kvm/main.c

+14 −0
Original line number Diff line number Diff line
@@ -15,6 +15,18 @@ 
#include <asm/kvm_nacl.h>

#include <asm/sbi.h>



DEFINE_STATIC_KEY_FALSE(kvm_riscv_vsstage_tlb_no_gpa);



static void kvm_riscv_setup_vendor_features(void)

{

	/* Andes AX66: split two-stage TLBs */

	if (riscv_cached_mvendorid(0) == ANDES_VENDOR_ID &&

	    (riscv_cached_marchid(0) & 0xFFFF) == 0x8A66) {

		static_branch_enable(&kvm_riscv_vsstage_tlb_no_gpa);

		kvm_info("VS-stage TLB does not cache guest physical address and VMID\n");

	}

}



long kvm_arch_dev_ioctl(struct file *filp,

			unsigned int ioctl, unsigned long arg)

{
@@ -160,6 +172,8 @@ static int __init riscv_kvm_init(void) 
		kvm_info("AIA available with %d guest external interrupts\n",

			 kvm_riscv_aia_nr_hgei);



	kvm_riscv_setup_vendor_features();



	kvm_register_perf_callbacks(NULL);



	rc = kvm_init(sizeof(struct kvm_vcpu), 0, THIS_MODULE);

arch/riscv/kvm/tlb.c

+30 −0
Original line number Diff line number Diff line
@@ -158,6 +158,36 @@ void kvm_riscv_local_hfence_vvma_all(unsigned long vmid) 
	csr_write(CSR_HGATP, hgatp);

}



void kvm_riscv_local_tlb_sanitize(struct kvm_vcpu *vcpu)

{

	unsigned long vmid;



	if (!kvm_riscv_gstage_vmid_bits() ||

	    vcpu->arch.last_exit_cpu == vcpu->cpu)

		return;



	/*

	 * On RISC-V platforms with hardware VMID support, we share same

	 * VMID for all VCPUs of a particular Guest/VM. This means we might

	 * have stale G-stage TLB entries on the current Host CPU due to

	 * some other VCPU of the same Guest which ran previously on the

	 * current Host CPU.

	 *

	 * To cleanup stale TLB entries, we simply flush all G-stage TLB

	 * entries by VMID whenever underlying Host CPU changes for a VCPU.

	 */



	vmid = READ_ONCE(vcpu->kvm->arch.vmid.vmid);

	kvm_riscv_local_hfence_gvma_vmid_all(vmid);



	/*

	 * Flush VS-stage TLB entries for implementation where VS-stage

	 * TLB does not cahce guest physical address and VMID.

	 */

	if (static_branch_unlikely(&kvm_riscv_vsstage_tlb_no_gpa))

		kvm_riscv_local_hfence_vvma_all(vmid);

}



void kvm_riscv_fence_i_process(struct kvm_vcpu *vcpu)

{

	kvm_riscv_vcpu_pmu_incr_fw(vcpu, SBI_PMU_FW_FENCE_I_RCVD);