Commit 32a120f5 authored by Imre Deak's avatar Imre Deak
Browse files

drm/i915/mtl: Skip PLL state verification in TBT mode 

In TBT-alt mode the driver doesn't program the PHY's PLL, which is
handled instead by Thunderbolt driver/FW components, hence the PLL's HW
vs. SW state verification should be skipped. During HW readout set a flag
in the PLL state if the port was at the moment in TBT-alt mode and skip
the verification of PLL parameters in this case.

Fixes: 45fe957a ("drm/i915/display: Add compare config for MTL+ platforms")
Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11258


Cc: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: default avatarMika Kahola <mika.kahola@intel.com>
Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240626170813.806470-1-imre.deak@intel.com
parent a9422ec9

drivers/gpu/drm/i915/display/intel_cx0_phy.c

+8 −3
Original line number Diff line number Diff line
@@ -3279,6 +3279,10 @@ void intel_cx0pll_readout_hw_state(struct intel_encoder *encoder, 
{

	pll_state->use_c10 = false;



	pll_state->tbt_mode = intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder));

	if (pll_state->tbt_mode)

		return;



	if (intel_encoder_is_c10phy(encoder)) {

		intel_c10pll_readout_hw_state(encoder, &pll_state->c10);

		pll_state->use_c10 = true;
@@ -3325,6 +3329,8 @@ static bool mtl_compare_hw_state_c20(const struct intel_c20pll_state *a, 
bool intel_cx0pll_compare_hw_state(const struct intel_cx0pll_state *a,

				   const struct intel_cx0pll_state *b)

{

	if (a->tbt_mode || b->tbt_mode)

		return true;



	if (a->use_c10 != b->use_c10)

		return false;
@@ -3420,12 +3426,11 @@ void intel_cx0pll_state_verify(struct intel_atomic_state *state, 
		return;



	encoder = intel_get_crtc_new_encoder(state, new_crtc_state);

	intel_cx0pll_readout_hw_state(encoder, &mpll_hw_state);



	if (intel_tc_port_in_tbt_alt_mode(enc_to_dig_port(encoder)))

	if (mpll_hw_state.tbt_mode)

		return;



	intel_cx0pll_readout_hw_state(encoder, &mpll_hw_state);



	if (intel_encoder_is_c10phy(encoder))

		intel_c10pll_state_verify(new_crtc_state, crtc, encoder, &mpll_hw_state.c10);

	else

drivers/gpu/drm/i915/display/intel_ddi.c

+3 −5
Original line number Diff line number Diff line
@@ -4027,14 +4027,12 @@ void intel_ddi_get_clock(struct intel_encoder *encoder, 
static void mtl_ddi_get_config(struct intel_encoder *encoder,

			       struct intel_crtc_state *crtc_state)

{

	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);

	intel_cx0pll_readout_hw_state(encoder, &crtc_state->dpll_hw_state.cx0pll);



	if (intel_tc_port_in_tbt_alt_mode(dig_port)) {

	if (crtc_state->dpll_hw_state.cx0pll.tbt_mode)

		crtc_state->port_clock = intel_mtl_tbt_calc_port_clock(encoder);

	} else {

		intel_cx0pll_readout_hw_state(encoder, &crtc_state->dpll_hw_state.cx0pll);

	else

		crtc_state->port_clock = intel_cx0pll_calc_port_clock(encoder, &crtc_state->dpll_hw_state.cx0pll);

	}



	intel_ddi_get_config(encoder, crtc_state);

}

drivers/gpu/drm/i915/display/intel_dpll_mgr.h

+1 −0
Original line number Diff line number Diff line
@@ -265,6 +265,7 @@ struct intel_cx0pll_state { 
	};

	bool ssc_enabled;

	bool use_c10;

	bool tbt_mode;

};



struct intel_dpll_hw_state {