Commit 3346c566 authored by Catalin Marinas's avatar Catalin Marinas
Browse files

Merge branches 'for-next/cpufeature', 'for-next/misc', 'for-next/kselftest',... 

Merge branches 'for-next/cpufeature', 'for-next/misc', 'for-next/kselftest', 'for-next/mte', 'for-next/errata', 'for-next/acpi', 'for-next/gic-v3-pmr' and 'for-next/doc', remote-tracking branch 'arm64/for-next/perf' into for-next/core

* arm64/for-next/perf:
  perf: add missing MODULE_DESCRIPTION() macros
  perf: arm_pmuv3: Include asm/arm_pmuv3.h from linux/perf/arm_pmuv3.h
  perf: arm_v6/7_pmu: Drop non-DT probe support
  perf/arm: Move 32-bit PMU drivers to drivers/perf/
  perf: arm_pmuv3: Drop unnecessary IS_ENABLED(CONFIG_ARM64) check
  perf: arm_pmuv3: Avoid assigning fixed cycle counter with threshold
  perf: imx_perf: add support for i.MX95 platform
  perf: imx_perf: fix counter start and config sequence
  perf: imx_perf: refactor driver for imx93
  perf: imx_perf: let the driver manage the counter usage rather the user
  perf: imx_perf: add macro definitions for parsing config attr
  dt-bindings: perf: fsl-imx-ddr: Add i.MX95 compatible
  perf: pmuv3: Add new Cortex and Neoverse PMUs
  dt-bindings: arm: pmu: Add new Cortex and Neoverse cores
  perf/arm-cmn: Enable support for tertiary match group
  perf/arm-cmn: Decouple wp_config registers from filter group number

* for-next/cpufeature:
  : Various cpufeature infrastructure patches
  arm64/cpufeature: Replace custom macros with fields from ID_AA64PFR0_EL1
  KVM: arm64: Replace custom macros with fields from ID_AA64PFR0_EL1
  arm64/cpufeatures/kvm: Add ARMv8.9 FEAT_ECBHB bits in ID_AA64MMFR1 register

* for-next/misc:
  : Miscellaneous patches
  arm64: smp: Fix missing IPI statistics
  arm64: Cleanup __cpu_set_tcr_t0sz()
  arm64/mm: Stop using ESR_ELx_FSC_TYPE during fault
  arm64: Kconfig: fix typo in __builtin_return_adddress
  ARM64: reloc_test: add missing MODULE_DESCRIPTION() macro
  arm64: implement raw_smp_processor_id() using thread_info
  arm64/arch_timer: include <linux/percpu.h>

* for-next/kselftest:
  : arm64 kselftest updates
  selftests: arm64: tags: remove the result script
  selftests: arm64: tags_test: conform test to TAP output
  kselftest/arm64: Fix a couple of spelling mistakes
  kselftest/arm64: Fix redundancy of a testcase
  kselftest/arm64: Include kernel mode NEON in fp-stress

* for-next/mte:
  : MTE updates
  arm64: mte: Make mte_check_tfsr_*() conditional on KASAN instead of MTE

* for-next/errata:
  : Arm CPU errata workarounds
  arm64: errata: Expand speculative SSBS workaround
  arm64: errata: Unify speculative SSBS errata logic
  arm64: cputype: Add Cortex-X925 definitions
  arm64: cputype: Add Cortex-A720 definitions
  arm64: cputype: Add Cortex-X3 definitions

* for-next/acpi:
  : arm64 ACPI patches
  ACPI: Add acpi=nospcr to disable ACPI SPCR as default console on ARM64
  ACPI / amba: Drop unnecessary check for registered amba_dummy_clk
  arm64: FFH: Move ACPI specific code into drivers/acpi/arm64/
  arm64: cpuidle: Move ACPI specific code into drivers/acpi/arm64/
  ACPI: arm64: Sort entries alphabetically

* for-next/gic-v3-pmr:
  : arm64: irqchip/gic-v3: Use compiletime constant PMR values
  arm64: irqchip/gic-v3: Select priorities at boot time
  irqchip/gic-v3: Detect GICD_CTRL.DS and SCR_EL3.FIQ earlier
  irqchip/gic-v3: Make distributor priorities variables
  irqchip/gic-common: Remove sync_access callback
  wordpart.h: Add REPEAT_BYTE_U32()

* for-next/doc:
  : arm64 documentation updates
  Documentation: arm64: Update memory.rst for TBI
parents 42bebc7c 056600ff 916b93f4 6e3bc73b 26ca4423 75b3c43e f5a4af3c 18fdb634 5e30c16b

Documentation/admin-guide/kernel-parameters.txt

+7 −3
Original line number Diff line number Diff line
@@ -12,7 +12,7 @@ 
	acpi=		[HW,ACPI,X86,ARM64,RISCV64,EARLY]

			Advanced Configuration and Power Interface

			Format: { force | on | off | strict | noirq | rsdt |

				  copy_dsdt }

				  copy_dsdt | nospcr }

			force -- enable ACPI if default was off

			on -- enable ACPI but allow fallback to DT [arm64,riscv64]

			off -- disable ACPI if default was on
@@ -21,8 +21,12 @@ 
				strictly ACPI specification compliant.

			rsdt -- prefer RSDT over (default) XSDT

			copy_dsdt -- copy DSDT to memory

			For ARM64 and RISCV64, ONLY "acpi=off", "acpi=on" or

			"acpi=force" are available

			nospcr -- disable console in ACPI SPCR table as

				default _serial_ console on ARM64

			For ARM64, ONLY "acpi=off", "acpi=on", "acpi=force" or

			"acpi=nospcr" are available

			For RISCV64, ONLY "acpi=off", "acpi=on" or "acpi=force"

			are available



			See also Documentation/power/runtime_pm.rst, pci=noacpi

Documentation/arch/arm64/memory.rst

+20 −22
Original line number Diff line number Diff line
@@ -18,12 +18,10 @@ ARMv8.2 adds optional support for Large Virtual Address space. This is 
only available when running with a 64KB page size and expands the

number of descriptors in the first level of translation.



User addresses have bits 63:48 set to 0 while the kernel addresses have

the same bits set to 1. TTBRx selection is given by bit 63 of the

virtual address. The swapper_pg_dir contains only kernel (global)

mappings while the user pgd contains only user (non-global) mappings.

The swapper_pg_dir address is written to TTBR1 and never written to

TTBR0.

TTBRx selection is given by bit 55 of the virtual address. The

swapper_pg_dir contains only kernel (global) mappings while the user pgd

contains only user (non-global) mappings.  The swapper_pg_dir address is

written to TTBR1 and never written to TTBR0.





AArch64 Linux memory layout with 4KB pages + 4 levels (48-bit)::
@@ -72,7 +70,7 @@ Translation table lookup with 4KB pages:: 
            |        |         |         +-----------> [29:21] L2 index

            |        |         +---------------------> [38:30] L1 index

            |        +-------------------------------> [47:39] L0 index

   +-------------------------------------------------> [63] TTBR0/1

            +----------------------------------------> [55] TTBR0/1





Translation table lookup with 64KB pages::
@@ -87,7 +85,7 @@ Translation table lookup with 64KB pages:: 
            |        |    +--------------------------> [41:29] L2 index

            |        +-------------------------------> [47:42] L1 index (48-bit)

            |                                          [51:42] L1 index (52-bit)

   +-------------------------------------------------> [63] TTBR0/1

            +----------------------------------------> [55] TTBR0/1





When using KVM without the Virtualization Host Extensions, the

Documentation/arch/arm64/silicon-errata.rst

+15 −1
Original line number Diff line number Diff line
@@ -132,16 +132,26 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A710     | #2224489        | ARM64_ERRATUM_2224489       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A710     | #3324338        | ARM64_ERRATUM_3194386       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A715     | #2645198        | ARM64_ERRATUM_2645198       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-A720     | #3456091        | ARM64_ERRATUM_3194386       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-X1       | #1502854        | N/A                         |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-X2       | #2119858        | ARM64_ERRATUM_2119858       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-X2       | #2224489        | ARM64_ERRATUM_2224489       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-X2       | #3324338        | ARM64_ERRATUM_3194386       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-X3       | #3324335        | ARM64_ERRATUM_3194386       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-X4       | #3194386        | ARM64_ERRATUM_3194386       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Cortex-X925     | #3324334        | ARM64_ERRATUM_3194386       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-N1     | #1188873,1418040| ARM64_ERRATUM_1418040       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-N1     | #1349291        | N/A                         |
@@ -156,9 +166,13 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-N2     | #2253138        | ARM64_ERRATUM_2253138       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-N2     | #3324339        | ARM64_ERRATUM_3194386       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-V1     | #1619801        | N/A                         |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-V3     | #3312417        | ARM64_ERRATUM_3312417       |

| ARM            | Neoverse-V2     | #3324336        | ARM64_ERRATUM_3194386       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | Neoverse-V3     | #3312417        | ARM64_ERRATUM_3194386       |

+----------------+-----------------+-----------------+-----------------------------+

| ARM            | MMU-500         | #841119,826419  | N/A                         |

+----------------+-----------------+-----------------+-----------------------------+

arch/arm64/Kconfig

+12 −26
Original line number Diff line number Diff line
@@ -381,7 +381,7 @@ config BROKEN_GAS_INST 


config BUILTIN_RETURN_ADDRESS_STRIPS_PAC

	bool

	# Clang's __builtin_return_adddress() strips the PAC since 12.0.0

	# Clang's __builtin_return_address() strips the PAC since 12.0.0

	# https://github.com/llvm/llvm-project/commit/2a96f47c5ffca84cd774ad402cacd137f4bf45e2

	default y if CC_IS_CLANG

	# GCC's __builtin_return_address() strips the PAC since 11.1.0,
@@ -1067,34 +1067,21 @@ config ARM64_ERRATUM_3117295 


	  If unsure, say Y.



config ARM64_WORKAROUND_SPECULATIVE_SSBS

	bool



config ARM64_ERRATUM_3194386

	bool "Cortex-X4: 3194386: workaround for MSR SSBS not self-synchronizing"

	select ARM64_WORKAROUND_SPECULATIVE_SSBS

	bool "Cortex-{A720,X4,X925}/Neoverse-V3: workaround for MSR SSBS not self-synchronizing"

	default y

	help

	  This option adds the workaround for ARM Cortex-X4 erratum 3194386.

	  This option adds the workaround for the following errata:



	  On affected cores "MSR SSBS, #0" instructions may not affect

	  subsequent speculative instructions, which may permit unexepected

	  speculative store bypassing.



	  Work around this problem by placing a speculation barrier after

	  kernel changes to SSBS. The presence of the SSBS special-purpose

	  register is hidden from hwcaps and EL0 reads of ID_AA64PFR1_EL1, such

	  that userspace will use the PR_SPEC_STORE_BYPASS prctl to change

	  SSBS.



	  If unsure, say Y.



config ARM64_ERRATUM_3312417

	bool "Neoverse-V3: 3312417: workaround for MSR SSBS not self-synchronizing"

	select ARM64_WORKAROUND_SPECULATIVE_SSBS

	default y

	help

	  This option adds the workaround for ARM Neoverse-V3 erratum 3312417.

	  * ARM Cortex-A710 erratam 3324338

	  * ARM Cortex-A720 erratum 3456091

	  * ARM Cortex-X2 erratum 3324338

	  * ARM Cortex-X3 erratum 3324335

	  * ARM Cortex-X4 erratum 3194386

	  * ARM Cortex-X925 erratum 3324334

	  * ARM Neoverse N2 erratum 3324339

	  * ARM Neoverse V2 erratum 3324336

	  * ARM Neoverse-V3 erratum 3312417



	  On affected cores "MSR SSBS, #0" instructions may not affect

	  subsequent speculative instructions, which may permit unexepected
@@ -1108,7 +1095,6 @@ config ARM64_ERRATUM_3312417 


	  If unsure, say Y.





config CAVIUM_ERRATUM_22375

	bool "Cavium erratum 22375, 24313"

	default y

arch/arm64/include/asm/arch_gicv3.h

+0 −15
Original line number Diff line number Diff line
@@ -175,21 +175,6 @@ static inline bool gic_prio_masking_enabled(void) 


static inline void gic_pmr_mask_irqs(void)

{

	BUILD_BUG_ON(GICD_INT_DEF_PRI < (__GIC_PRIO_IRQOFF |

					 GIC_PRIO_PSR_I_SET));

	BUILD_BUG_ON(GICD_INT_DEF_PRI >= GIC_PRIO_IRQON);

	/*

	 * Need to make sure IRQON allows IRQs when SCR_EL3.FIQ is cleared

	 * and non-secure PMR accesses are not subject to the shifts that

	 * are applied to IRQ priorities

	 */

	BUILD_BUG_ON((0x80 | (GICD_INT_DEF_PRI >> 1)) >= GIC_PRIO_IRQON);

	/*

	 * Same situation as above, but now we make sure that we can mask

	 * regular interrupts.

	 */

	BUILD_BUG_ON((0x80 | (GICD_INT_DEF_PRI >> 1)) < (__GIC_PRIO_IRQOFF_NS |

							 GIC_PRIO_PSR_I_SET));

	gic_write_pmr(GIC_PRIO_IRQOFF);

}