Commit 34267d3c authored by Miquel Raynal's avatar Miquel Raynal
Browse files

Merge tag 'spi-nor/for-6.13' of... 

Merge tag 'spi-nor/for-6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux into mtd/next

SPI NOR introduces byte swap support for 8D-8D-8D mode and a user for
it: macronix. SPI NOR flashes may swap the bytes on a 16-bit boundary
when configured in Octal DTR mode. For such cases the byte order is
propagated through SPI MEM to the SPI controllers so that the controllers
swap the bytes back at runtime. This avoids breaking the boot sequence
because of the endianness problems that appear when the bootloaders use
1-1-1 and the kernel uses 8D-8D-8D with byte swap support. Along with the
SPI MEM byte swap support we queue a patch for the SPI MXIC controller
that swaps the bytes back at runtime.

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parents f8470006 98d1fb94

drivers/mtd/spi-nor/core.c

+4 −1
Original line number Diff line number Diff line
@@ -89,7 +89,7 @@ void spi_nor_spimem_setup_op(const struct spi_nor *nor, 
		op->addr.buswidth = spi_nor_get_protocol_addr_nbits(proto);



	if (op->dummy.nbytes)

		op->dummy.buswidth = spi_nor_get_protocol_addr_nbits(proto);

		op->dummy.buswidth = spi_nor_get_protocol_data_nbits(proto);



	if (op->data.nbytes)

		op->data.buswidth = spi_nor_get_protocol_data_nbits(proto);
@@ -113,6 +113,9 @@ void spi_nor_spimem_setup_op(const struct spi_nor *nor, 
		op->cmd.opcode = (op->cmd.opcode << 8) | ext;

		op->cmd.nbytes = 2;

	}



	if (proto == SNOR_PROTO_8_8_8_DTR && nor->flags & SNOR_F_SWAP16)

		op->data.swap16 = true;

}



/**

drivers/mtd/spi-nor/core.h

+1 −0
Original line number Diff line number Diff line
@@ -140,6 +140,7 @@ enum spi_nor_option_flags { 
	SNOR_F_RWW		= BIT(14),

	SNOR_F_ECC		= BIT(15),

	SNOR_F_NO_WP		= BIT(16),

	SNOR_F_SWAP16		= BIT(17),

};



struct spi_nor_read_command {

drivers/mtd/spi-nor/macronix.c

+98 −1
Original line number Diff line number Diff line
@@ -8,6 +8,23 @@ 


#include "core.h"



#define MXIC_NOR_OP_RD_CR2	0x71		/* Read configuration register 2 opcode */

#define MXIC_NOR_OP_WR_CR2	0x72		/* Write configuration register 2 opcode */

#define MXIC_NOR_ADDR_CR2_MODE	0x00000000	/* CR2 address for setting spi/sopi/dopi mode */

#define MXIC_NOR_ADDR_CR2_DC	0x00000300	/* CR2 address for setting dummy cycles */

#define MXIC_NOR_REG_DOPI_EN	0x2		/* Enable Octal DTR */

#define MXIC_NOR_REG_SPI_EN	0x0		/* Enable SPI */



/* Convert dummy cycles to bit pattern */

#define MXIC_NOR_REG_DC(p) \

	((20 - (p)) >> 1)



#define MXIC_NOR_WR_CR2(addr, ndata, buf)			\

	SPI_MEM_OP(SPI_MEM_OP_CMD(MXIC_NOR_OP_WR_CR2, 0),	\

		   SPI_MEM_OP_ADDR(4, addr, 0),			\

		   SPI_MEM_OP_NO_DUMMY,				\

		   SPI_MEM_OP_DATA_OUT(ndata, buf, 0))



static int

mx25l25635_post_bfpt_fixups(struct spi_nor *nor,

			    const struct sfdp_parameter_header *bfpt_header,
@@ -182,9 +199,88 @@ static const struct flash_info macronix_nor_parts[] = { 
		.name = "mx25l3255e",

		.size = SZ_4M,

		.no_sfdp_flags = SECT_4K,

	}

	},

	/*

	 * This spares us of adding new flash entries for flashes that can be

	 * initialized solely based on the SFDP data, but still need the

	 * manufacturer hooks to set parameters that can't be discovered at SFDP

	 * parsing time.

	 */

	{ .id = SNOR_ID(0xc2) }

};



static int macronix_nor_octal_dtr_en(struct spi_nor *nor)

{

	struct spi_mem_op op;

	u8 *buf = nor->bouncebuf, i;

	int ret;



	/* Use dummy cycles which is parse by SFDP and convert to bit pattern. */

	buf[0] = MXIC_NOR_REG_DC(nor->params->reads[SNOR_CMD_READ_8_8_8_DTR].num_wait_states);

	op = (struct spi_mem_op)MXIC_NOR_WR_CR2(MXIC_NOR_ADDR_CR2_DC, 1, buf);

	ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto);

	if (ret)

		return ret;



	/* Set the octal and DTR enable bits. */

	buf[0] = MXIC_NOR_REG_DOPI_EN;

	op = (struct spi_mem_op)MXIC_NOR_WR_CR2(MXIC_NOR_ADDR_CR2_MODE, 1, buf);

	ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto);

	if (ret)

		return ret;



	/* Read flash ID to make sure the switch was successful. */

	ret = spi_nor_read_id(nor, 4, 4, buf, SNOR_PROTO_8_8_8_DTR);

	if (ret) {

		dev_dbg(nor->dev, "error %d reading JEDEC ID after enabling 8D-8D-8D mode\n", ret);

		return ret;

	}



	/* Macronix SPI-NOR flash 8D-8D-8D read ID would get 6 bytes data A-A-B-B-C-C */

	for (i = 0; i < nor->info->id->len; i++)

		if (buf[i * 2] != buf[(i * 2) + 1] || buf[i * 2] != nor->info->id->bytes[i])

			return -EINVAL;



	return 0;

}



static int macronix_nor_octal_dtr_dis(struct spi_nor *nor)

{

	struct spi_mem_op op;

	u8 *buf = nor->bouncebuf;

	int ret;



	/*

	 * The register is 1-byte wide, but 1-byte transactions are not

	 * allowed in 8D-8D-8D mode. Since there is no register at the

	 * next location, just initialize the value to 0 and let the

	 * transaction go on.

	 */

	buf[0] = MXIC_NOR_REG_SPI_EN;

	buf[1] = 0x0;

	op = (struct spi_mem_op)MXIC_NOR_WR_CR2(MXIC_NOR_ADDR_CR2_MODE, 2, buf);

	ret = spi_nor_write_any_volatile_reg(nor, &op, SNOR_PROTO_8_8_8_DTR);

	if (ret)

		return ret;



	/* Read flash ID to make sure the switch was successful. */

	ret = spi_nor_read_id(nor, 0, 0, buf, SNOR_PROTO_1_1_1);

	if (ret) {

		dev_dbg(nor->dev, "error %d reading JEDEC ID after disabling 8D-8D-8D mode\n", ret);

		return ret;

	}



	if (memcmp(buf, nor->info->id->bytes, nor->info->id->len))

		return -EINVAL;



	return 0;

}



static int macronix_nor_set_octal_dtr(struct spi_nor *nor, bool enable)

{

	return enable ? macronix_nor_octal_dtr_en(nor) : macronix_nor_octal_dtr_dis(nor);

}



static void macronix_nor_default_init(struct spi_nor *nor)

{

	nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable;
@@ -194,6 +290,7 @@ static int macronix_nor_late_init(struct spi_nor *nor) 
{

	if (!nor->params->set_4byte_addr_mode)

		nor->params->set_4byte_addr_mode = spi_nor_set_4byte_addr_mode_en4b_ex4b;

	nor->params->set_octal_dtr = macronix_nor_set_octal_dtr;



	return 0;

}

drivers/mtd/spi-nor/sfdp.c

+4 −0
Original line number Diff line number Diff line
@@ -671,6 +671,10 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor, 
		return -EOPNOTSUPP;

	}



	/* Byte order in 8D-8D-8D mode */

	if (bfpt.dwords[SFDP_DWORD(18)] & BFPT_DWORD18_BYTE_ORDER_SWAPPED)

		nor->flags |= SNOR_F_SWAP16;



	return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt);

}

drivers/mtd/spi-nor/sfdp.h

+1 −0
Original line number Diff line number Diff line
@@ -130,6 +130,7 @@ struct sfdp_bfpt { 
#define BFPT_DWORD18_CMD_EXT_INV		(0x1UL << 29) /* Invert */

#define BFPT_DWORD18_CMD_EXT_RES		(0x2UL << 29) /* Reserved */

#define BFPT_DWORD18_CMD_EXT_16B		(0x3UL << 29) /* 16-bit opcode */

#define BFPT_DWORD18_BYTE_ORDER_SWAPPED		BIT(31)	/* Byte order swapped in 8D-8D-8D mode */



struct sfdp_parameter_header {

	u8		id_lsb;