Commit 34a40731 authored by Viken Dadhaniya's avatar Viken Dadhaniya Committed by Bjorn Andersson
Browse files

arm64: dts: qcom: sa8775p: Populate additional UART DT nodes 



Currently, UART configuration is populated for only a few SEs
(Serial Engines) in the sa8775p DTSI file. Since every SE can
support the UART protocol, usecase or client should have the flexibility
to enable required SE for UART depending on the specific board version.

Hence, populate UART configurations for the remaining SEs in the
sa8775p SoC.

Co-developed-by: default avatarMukesh Kumar Savaliya <quic_msavaliy@quicinc.com>
Signed-off-by: default avatarMukesh Kumar Savaliya <quic_msavaliy@quicinc.com>
Signed-off-by: default avatarViken Dadhaniya <quic_vdadhani@quicinc.com>
Link: https://lore.kernel.org/r/20241007091407.13798-1-quic_vdadhani@quicinc.com


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent 8847c970

arch/arm64/boot/dts/qcom/sa8775p.dtsi

+231 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: BSD-3-Clause

/*

 * Copyright (c) 2023, Linaro Limited

 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.

 */



#include <dt-bindings/interconnect/qcom,icc.h>
@@ -905,6 +906,21 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 
				status = "disabled";

			};



			uart14: serial@880000 {

				compatible = "qcom,geni-uart";

				reg = <0x0 0x00880000 0x0 0x4000>;

				interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;

				clock-names = "se";

				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS

						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,

						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS

						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;

				interconnect-names = "qup-core", "qup-config";

				power-domains = <&rpmhpd SA8775P_CX>;

				status = "disabled";

			};



			i2c15: i2c@884000 {

				compatible = "qcom,geni-i2c";

				reg = <0x0 0x884000 0x0 0x4000>;
@@ -947,6 +963,21 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 
				status = "disabled";

			};



			uart15: serial@884000 {

				compatible = "qcom,geni-uart";

				reg = <0x0 0x00884000 0x0 0x4000>;

				interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;

				clock-names = "se";

				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS

						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,

						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS

						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;

				interconnect-names = "qup-core", "qup-config";

				power-domains = <&rpmhpd SA8775P_CX>;

				status = "disabled";

			};



			i2c16: i2c@888000 {

				compatible = "qcom,geni-i2c";

				reg = <0x0 0x888000 0x0 0x4000>;
@@ -989,6 +1020,21 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 
				status = "disabled";

			};



			uart16: serial@888000 {

				compatible = "qcom,geni-uart";

				reg = <0x0 0x00888000 0x0 0x4000>;

				interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;

				clock-names = "se";

				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS

						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,

						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS

						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;

				interconnect-names = "qup-core", "qup-config";

				power-domains = <&rpmhpd SA8775P_CX>;

				status = "disabled";

			};



			i2c17: i2c@88c000 {

				compatible = "qcom,geni-i2c";

				reg = <0x0 0x88c000 0x0 0x4000>;
@@ -1088,6 +1134,21 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 
				status = "disabled";

			};



			uart18: serial@890000 {

				compatible = "qcom,geni-uart";

				reg = <0x0 0x00890000 0x0 0x4000>;

				interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;

				clock-names = "se";

				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS

						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,

						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS

						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;

				interconnect-names = "qup-core", "qup-config";

				power-domains = <&rpmhpd SA8775P_CX>;

				status = "disabled";

			};



			i2c19: i2c@894000 {

				compatible = "qcom,geni-i2c";

				reg = <0x0 0x894000 0x0 0x4000>;
@@ -1130,6 +1191,21 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 
				status = "disabled";

			};



			uart19: serial@894000 {

				compatible = "qcom,geni-uart";

				reg = <0x0 0x00894000 0x0 0x4000>;

				interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;

				clock-names = "se";

				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS

						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,

						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS

						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;

				interconnect-names = "qup-core", "qup-config";

				power-domains = <&rpmhpd SA8775P_CX>;

				status = "disabled";

			};



			i2c20: i2c@898000 {

				compatible = "qcom,geni-i2c";

				reg = <0x0 0x898000 0x0 0x4000>;
@@ -1171,6 +1247,22 @@ &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 
				power-domains = <&rpmhpd SA8775P_CX>;

				status = "disabled";

			};



			uart20: serial@898000 {

				compatible = "qcom,geni-uart";

				reg = <0x0 0x00898000 0x0 0x4000>;

				interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;

				clock-names = "se";

				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS

						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,

						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS

						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>;

				interconnect-names = "qup-core", "qup-config";

				power-domains = <&rpmhpd SA8775P_CX>;

				status = "disabled";

			};



		};



		qupv3_id_0: geniqup@9c0000 {
@@ -1227,6 +1319,21 @@ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 
				status = "disabled";

			};



			uart0: serial@980000 {

				compatible = "qcom,geni-uart";

				reg = <0x0 0x980000 0x0 0x4000>;

				interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;

				clock-names = "se";

				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS

						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,

						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS

						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;

				interconnect-names = "qup-core", "qup-config";

				power-domains = <&rpmhpd SA8775P_CX>;

				status = "disabled";

			};



			i2c1: i2c@984000 {

				compatible = "qcom,geni-i2c";

				reg = <0x0 0x984000 0x0 0x4000>;
@@ -1269,6 +1376,21 @@ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 
				status = "disabled";

			};



			uart1: serial@984000 {

				compatible = "qcom,geni-uart";

				reg = <0x0 0x984000 0x0 0x4000>;

				interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;

				clock-names = "se";

				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS

						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,

						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS

						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;

				interconnect-names = "qup-core", "qup-config";

				power-domains = <&rpmhpd SA8775P_CX>;

				status = "disabled";

			};



			i2c2: i2c@988000 {

				compatible = "qcom,geni-i2c";

				reg = <0x0 0x988000 0x0 0x4000>;
@@ -1311,6 +1433,21 @@ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 
				status = "disabled";

			};



			uart2: serial@988000 {

				compatible = "qcom,geni-uart";

				reg = <0x0 0x988000 0x0 0x4000>;

				interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;

				clock-names = "se";

				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS

						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,

						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS

						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;

				interconnect-names = "qup-core", "qup-config";

				power-domains = <&rpmhpd SA8775P_CX>;

				status = "disabled";

			};



			i2c3: i2c@98c000 {

				compatible = "qcom,geni-i2c";

				reg = <0x0 0x98c000 0x0 0x4000>;
@@ -1353,6 +1490,21 @@ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 
				status = "disabled";

			};



			uart3: serial@98c000 {

				compatible = "qcom,geni-uart";

				reg = <0x0 0x98c000 0x0 0x4000>;

				interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;

				clock-names = "se";

				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS

						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,

						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS

						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;

				interconnect-names = "qup-core", "qup-config";

				power-domains = <&rpmhpd SA8775P_CX>;

				status = "disabled";

			};



			i2c4: i2c@990000 {

				compatible = "qcom,geni-i2c";

				reg = <0x0 0x990000 0x0 0x4000>;
@@ -1395,6 +1547,21 @@ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 
				status = "disabled";

			};



			uart4: serial@990000 {

				compatible = "qcom,geni-uart";

				reg = <0x0 0x990000 0x0 0x4000>;

				interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>;

				clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;

				clock-names = "se";

				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS

						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,

						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS

						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;

				interconnect-names = "qup-core", "qup-config";

				power-domains = <&rpmhpd SA8775P_CX>;

				status = "disabled";

			};



			i2c5: i2c@994000 {

				compatible = "qcom,geni-i2c";

				reg = <0x0 0x994000 0x0 0x4000>;
@@ -1507,6 +1674,22 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 
				status = "disabled";

			};



			uart7: serial@a80000 {

				compatible = "qcom,geni-uart";

				reg = <0x0 0x00a80000 0x0 0x4000>;

				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;

				clock-names = "se";

				clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;

				interconnect-names = "qup-core", "qup-config";

				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS

						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,

						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS

						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;

				power-domains = <&rpmhpd SA8775P_CX>;

				operating-points-v2 = <&qup_opp_table_100mhz>;

				status = "disabled";

			};



			i2c8: i2c@a84000 {

				compatible = "qcom,geni-i2c";

				reg = <0x0 0xa84000 0x0 0x4000>;
@@ -1549,6 +1732,22 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 
				status = "disabled";

			};



			uart8: serial@a84000 {

				compatible = "qcom,geni-uart";

				reg = <0x0 0x00a84000 0x0 0x4000>;

				interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;

				clock-names = "se";

				clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;

				interconnect-names = "qup-core", "qup-config";

				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS

						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,

						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS

						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;

				power-domains = <&rpmhpd SA8775P_CX>;

				operating-points-v2 = <&qup_opp_table_100mhz>;

				status = "disabled";

			};



			i2c9: i2c@a88000 {

				compatible = "qcom,geni-i2c";

				reg = <0x0 0xa88000 0x0 0x4000>;
@@ -1706,6 +1905,22 @@ &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 
				status = "disabled";

			};



			uart11: serial@a90000 {

				compatible = "qcom,geni-uart";

				reg = <0x0 0x00a90000 0x0 0x4000>;

				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;

				clock-names = "se";

				clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;

				interconnect-names = "qup-core", "qup-config";

				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS

						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,

						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS

						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>;

				power-domains = <&rpmhpd SA8775P_CX>;

				operating-points-v2 = <&qup_opp_table_100mhz>;

				status = "disabled";

			};



			i2c12: i2c@a94000 {

				compatible = "qcom,geni-i2c";

				reg = <0x0 0xa94000 0x0 0x4000>;
@@ -1838,6 +2053,22 @@ &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>, 
				power-domains = <&rpmhpd SA8775P_CX>;

				status = "disabled";

			};



			uart21: serial@b80000 {

				compatible = "qcom,geni-uart";

				reg = <0x0 0x00b80000 0x0 0x4000>;

				interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>;

				clock-names = "se";

				clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>;

				interconnect-names = "qup-core", "qup-config";

				interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS

						 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>,

						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS

						 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>;

				power-domains = <&rpmhpd SA8775P_CX>;

				operating-points-v2 = <&qup_opp_table_100mhz>;

				status = "disabled";

			};

		};



		rng: rng@10d2000 {