Loading drivers/thunderbolt/clx.c +22 −22 Original line number Diff line number Diff line Loading @@ -174,6 +174,28 @@ bool tb_port_clx_is_enabled(struct tb_port *port, unsigned int clx) return !!(tb_port_clx(port) & clx); } /** * tb_switch_clx_is_supported() - Is CLx supported on this type of router * @sw: The router to check CLx support for */ static bool tb_switch_clx_is_supported(const struct tb_switch *sw) { if (!clx_enabled) return false; if (sw->quirks & QUIRK_NO_CLX) return false; /* * CLx is not enabled and validated on Intel USB4 platforms * before Alder Lake. */ if (tb_switch_is_tiger_lake(sw)) return false; return tb_switch_is_usb4(sw) || tb_switch_is_titan_ridge(sw); } /** * tb_switch_clx_init() - Initialize router CL states * @sw: Router Loading Loading @@ -273,28 +295,6 @@ static int tb_switch_mask_clx_objections(struct tb_switch *sw) sw->cap_lp + offset, ARRAY_SIZE(val)); } /** * tb_switch_clx_is_supported() - Is CLx supported on this type of router * @sw: The router to check CLx support for */ bool tb_switch_clx_is_supported(const struct tb_switch *sw) { if (!clx_enabled) return false; if (sw->quirks & QUIRK_NO_CLX) return false; /* * CLx is not enabled and validated on Intel USB4 platforms * before Alder Lake. */ if (tb_switch_is_tiger_lake(sw)) return false; return tb_switch_is_usb4(sw) || tb_switch_is_titan_ridge(sw); } static bool validate_mask(unsigned int clx) { /* Previous states need to be enabled */ Loading drivers/thunderbolt/tb.h +0 −1 Original line number Diff line number Diff line Loading @@ -1001,7 +1001,6 @@ static inline bool tb_switch_tmu_is_enabled(const struct tb_switch *sw) bool tb_port_clx_is_enabled(struct tb_port *port, unsigned int clx); int tb_switch_clx_init(struct tb_switch *sw); bool tb_switch_clx_is_supported(const struct tb_switch *sw); int tb_switch_clx_enable(struct tb_switch *sw, unsigned int clx); int tb_switch_clx_disable(struct tb_switch *sw); Loading Loading
drivers/thunderbolt/clx.c +22 −22 Original line number Diff line number Diff line Loading @@ -174,6 +174,28 @@ bool tb_port_clx_is_enabled(struct tb_port *port, unsigned int clx) return !!(tb_port_clx(port) & clx); } /** * tb_switch_clx_is_supported() - Is CLx supported on this type of router * @sw: The router to check CLx support for */ static bool tb_switch_clx_is_supported(const struct tb_switch *sw) { if (!clx_enabled) return false; if (sw->quirks & QUIRK_NO_CLX) return false; /* * CLx is not enabled and validated on Intel USB4 platforms * before Alder Lake. */ if (tb_switch_is_tiger_lake(sw)) return false; return tb_switch_is_usb4(sw) || tb_switch_is_titan_ridge(sw); } /** * tb_switch_clx_init() - Initialize router CL states * @sw: Router Loading Loading @@ -273,28 +295,6 @@ static int tb_switch_mask_clx_objections(struct tb_switch *sw) sw->cap_lp + offset, ARRAY_SIZE(val)); } /** * tb_switch_clx_is_supported() - Is CLx supported on this type of router * @sw: The router to check CLx support for */ bool tb_switch_clx_is_supported(const struct tb_switch *sw) { if (!clx_enabled) return false; if (sw->quirks & QUIRK_NO_CLX) return false; /* * CLx is not enabled and validated on Intel USB4 platforms * before Alder Lake. */ if (tb_switch_is_tiger_lake(sw)) return false; return tb_switch_is_usb4(sw) || tb_switch_is_titan_ridge(sw); } static bool validate_mask(unsigned int clx) { /* Previous states need to be enabled */ Loading
drivers/thunderbolt/tb.h +0 −1 Original line number Diff line number Diff line Loading @@ -1001,7 +1001,6 @@ static inline bool tb_switch_tmu_is_enabled(const struct tb_switch *sw) bool tb_port_clx_is_enabled(struct tb_port *port, unsigned int clx); int tb_switch_clx_init(struct tb_switch *sw); bool tb_switch_clx_is_supported(const struct tb_switch *sw); int tb_switch_clx_enable(struct tb_switch *sw, unsigned int clx); int tb_switch_clx_disable(struct tb_switch *sw); Loading