Commit 3666ed82 authored by Jay Cornwall's avatar Jay Cornwall Committed by Alex Deucher
Browse files

drm/amdgpu: Increase KIQ invalidate_tlbs timeout 



KIQ invalidate_tlbs request has been seen to marginally exceed the
configured 100 ms timeout on systems under load.

All other KIQ requests in the driver use a 10 second timeout. Use a
similar timeout implementation on the invalidate_tlbs path.

v2: Poll once before msleep
v3: Fix return value

Signed-off-by: default avatarJay Cornwall <jay.cornwall@amd.com>
Cc: Kent Russell <kent.russell@amd.com>
Reviewed-by: default avatarHarish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent b3862d60

drivers/gpu/drm/amd/amdgpu/amdgpu.h

+0 −1
Original line number Diff line number Diff line
@@ -353,7 +353,6 @@ enum amdgpu_kiq_irq { 
	AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,

	AMDGPU_CP_KIQ_IRQ_LAST

};

#define SRIOV_USEC_TIMEOUT  1200000 /* wait 12 * 100ms for SRIOV */

#define MAX_KIQ_REG_WAIT       5000 /* in usecs, 5ms */

#define MAX_KIQ_REG_BAILOUT_INTERVAL   5 /* in msecs, 5ms */

#define MAX_KIQ_REG_TRY 1000

drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c

+14 −5
Original line number Diff line number Diff line
@@ -699,12 +699,10 @@ int amdgpu_gmc_flush_gpu_tlb_pasid(struct amdgpu_device *adev, uint16_t pasid, 
				   uint32_t flush_type, bool all_hub,

				   uint32_t inst)

{

	u32 usec_timeout = amdgpu_sriov_vf(adev) ? SRIOV_USEC_TIMEOUT :

		adev->usec_timeout;

	struct amdgpu_ring *ring = &adev->gfx.kiq[inst].ring;

	struct amdgpu_kiq *kiq = &adev->gfx.kiq[inst];

	unsigned int ndw;

	int r;

	int r, cnt = 0;

	uint32_t seq;



	/*
@@ -761,10 +759,21 @@ int amdgpu_gmc_flush_gpu_tlb_pasid(struct amdgpu_device *adev, uint16_t pasid, 


		amdgpu_ring_commit(ring);

		spin_unlock(&adev->gfx.kiq[inst].ring_lock);

		if (amdgpu_fence_wait_polling(ring, seq, usec_timeout) < 1) {



		r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);



		might_sleep();

		while (r < 1 && cnt++ < MAX_KIQ_REG_TRY &&

		       !amdgpu_reset_pending(adev->reset_domain)) {

			msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);

			r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);

		}



		if (cnt > MAX_KIQ_REG_TRY) {

			dev_err(adev->dev, "timeout waiting for kiq fence\n");

			r = -ETIME;

		}

		} else

			r = 0;

	}



error_unlock_reset: