Commit 36a7c96b authored by Michal Simek's avatar Michal Simek Committed by Rob Herring
Browse files

dt-bindings: fpga: Convert bridge binding to yaml 



Convert the generic fpga bridge DT binding to json-schema.

Signed-off-by: default avatarMichal Simek <michal.simek@amd.com>
Reviewed-by: default avatarXu Yilun <yilun.xu@intel.com>
Reviewed-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/14558a4dcfab5255c1683015287e9c7f48b1afc2.1704807147.git.michal.simek@amd.com


Signed-off-by: default avatarRob Herring <robh@kernel.org>
parent 9defbb1b

Documentation/devicetree/bindings/fpga/fpga-bridge.txt

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+0 −13
Original line number Diff line number Diff line 
FPGA Bridge Device Tree Binding



Optional properties:

- bridge-enable		: 0 if driver should disable bridge at startup

			  1 if driver should enable bridge at startup

			  Default is to leave bridge in current state.



Example:

	fpga_bridge3: fpga-bridge@ffc25080 {

		compatible = "altr,socfpga-fpga2sdram-bridge";

		reg = <0xffc25080 0x4>;

		bridge-enable = <0>;

	};

Documentation/devicetree/bindings/fpga/fpga-bridge.yaml

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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/fpga/fpga-bridge.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: FPGA Bridge



maintainers:

  - Michal Simek <michal.simek@amd.com>



properties:

  $nodename:

    pattern: "^fpga-bridge(@.*|-([0-9]|[1-9][0-9]+))?$"



  bridge-enable:

    description: |

      0 if driver should disable bridge at startup

      1 if driver should enable bridge at startup

      Default is to leave bridge in current state.

    $ref: /schemas/types.yaml#/definitions/uint32

    enum: [ 0, 1 ]



additionalProperties: true



examples:

  - |

    fpga-bridge {

        bridge-enable = <0>;

    };

Documentation/devicetree/bindings/fpga/xlnx,pr-decoupler.yaml

+4 −1
Original line number Diff line number Diff line
@@ -9,6 +9,9 @@ title: Xilinx LogiCORE Partial Reconfig Decoupler/AXI shutdown manager Softcore 
maintainers:

  - Nava kishore Manne <nava.kishore.manne@amd.com>



allOf:

  - $ref: fpga-bridge.yaml#



description: |

  The Xilinx LogiCORE Partial Reconfig(PR) Decoupler manages one or more

  decouplers/fpga bridges. The controller can decouple/disable the bridges
@@ -51,7 +54,7 @@ required: 
  - clocks

  - clock-names



additionalProperties: false

unevaluatedProperties: false



examples:

  - |