Unverified Commit 36f8960d authored by Clément Léger's avatar Clément Léger Committed by Palmer Dabbelt
Browse files

riscv: hwprobe: export Zimop ISA extension 



Export Zimop ISA extension through hwprobe.

Signed-off-by: default avatarClément Léger <cleger@rivosinc.com>
Reviewed-by: default avatarCharlie Jenkins <charlie@rivosinc.com>
Link: https://lore.kernel.org/r/20240619113529.676940-4-cleger@rivosinc.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent 2467c210

Documentation/arch/riscv/hwprobe.rst

+4 −0
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@@ -207,6 +207,10 @@ The following keys are defined: 
  * :c:macro:`RISCV_HWPROBE_EXT_ZVE64D`: The Vector sub-extension Zve64d is

    supported, as defined by version 1.0 of the RISC-V Vector extension manual.



  * :c:macro:`RISCV_HWPROBE_EXT_ZIMOP`: The Zimop May-Be-Operations extension is

       supported as defined in the RISC-V ISA manual starting from commit

       58220614a5f ("Zimop is ratified/1.0").



* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance

  information about the selected set of processors.

arch/riscv/include/uapi/asm/hwprobe.h

+1 −0
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@@ -65,6 +65,7 @@ struct riscv_hwprobe { 
#define		RISCV_HWPROBE_EXT_ZVE64X	(1ULL << 39)

#define		RISCV_HWPROBE_EXT_ZVE64F	(1ULL << 40)

#define		RISCV_HWPROBE_EXT_ZVE64D	(1ULL << 41)

#define		RISCV_HWPROBE_EXT_ZIMOP		(1ULL << 42)

#define RISCV_HWPROBE_KEY_CPUPERF_0	5

#define		RISCV_HWPROBE_MISALIGNED_UNKNOWN	(0 << 0)

#define		RISCV_HWPROBE_MISALIGNED_EMULATED	(1 << 0)

arch/riscv/kernel/sys_hwprobe.c

+1 −0
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@@ -112,6 +112,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, 
		EXT_KEY(ZACAS);

		EXT_KEY(ZICOND);

		EXT_KEY(ZIHINTPAUSE);

		EXT_KEY(ZIMOP);



		/*

		 * All the following extensions must depend on the kernel