Commit 370c2374 authored by Sai Krishna's avatar Sai Krishna Committed by Jakub Kicinski
Browse files

octeontx2-pf: CN20K mbox REQ/ACK implementation for NIC PF 



This implementation uses separate trigger interrupts for request,
response messages against using trigger message data in CN10K.
This patch adds support for basic mbox implementation for CN20K
from NIC PF side.

Signed-off-by: default avatarSai Krishna <saikrishnag@marvell.com>
Signed-off-by: default avatarSunil Kovvuri Goutham <sgoutham@marvell.com>
Signed-off-by: default avatarSubbaraya Sundeep <sbhatta@marvell.com>
Link: https://patch.msgid.link/1749639716-13868-5-git-send-email-sbhatta@marvell.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent f326d5d8

drivers/net/ethernet/marvell/octeontx2/af/cn20k/struct.h

+15 −0
Original line number Diff line number Diff line
@@ -8,6 +8,21 @@ 
#ifndef STRUCT_H

#define STRUCT_H



/*

 * CN20k RVU PF MBOX Interrupt Vector Enumeration

 *

 * Vectors 0 - 3 are compatible with pre cn20k and hence

 * existing macros are being reused.

 */

enum rvu_mbox_pf_int_vec_e {

	RVU_MBOX_PF_INT_VEC_VFPF_MBOX0	= 0x4,

	RVU_MBOX_PF_INT_VEC_VFPF_MBOX1	= 0x5,

	RVU_MBOX_PF_INT_VEC_VFPF1_MBOX0	= 0x6,

	RVU_MBOX_PF_INT_VEC_VFPF1_MBOX1	= 0x7,

	RVU_MBOX_PF_INT_VEC_AFPF_MBOX	= 0x8,

	RVU_MBOX_PF_INT_VEC_CNT		= 0x9,

};



/* RVU Admin function Interrupt Vector Enumeration */

enum rvu_af_cn20k_int_vec_e {

	RVU_AF_CN20K_INT_VEC_POISON		= 0x0,

drivers/net/ethernet/marvell/octeontx2/nic/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -8,7 +8,7 @@ obj-$(CONFIG_OCTEONTX2_VF) += rvu_nicvf.o otx2_ptp.o 
obj-$(CONFIG_RVU_ESWITCH) += rvu_rep.o



rvu_nicpf-y := otx2_pf.o otx2_common.o otx2_txrx.o otx2_ethtool.o \

               otx2_flows.o otx2_tc.o cn10k.o otx2_dmac_flt.o \

               otx2_flows.o otx2_tc.o cn10k.o cn20k.o otx2_dmac_flt.o \

               otx2_devlink.o qos_sq.o qos.o otx2_xsk.o

rvu_nicvf-y := otx2_vf.o

rvu_rep-y := rep.o

drivers/net/ethernet/marvell/octeontx2/nic/cn10k.c

+14 −4
Original line number Diff line number Diff line
@@ -14,6 +14,7 @@ static struct dev_hw_ops otx2_hw_ops = { 
	.sqe_flush = otx2_sqe_flush,

	.aura_freeptr = otx2_aura_freeptr,

	.refill_pool_ptrs = otx2_refill_pool_ptrs,

	.pfaf_mbox_intr_handler = otx2_pfaf_mbox_intr_handler,

};



static struct dev_hw_ops cn10k_hw_ops = {
@@ -21,8 +22,20 @@ static struct dev_hw_ops cn10k_hw_ops = { 
	.sqe_flush = cn10k_sqe_flush,

	.aura_freeptr = cn10k_aura_freeptr,

	.refill_pool_ptrs = cn10k_refill_pool_ptrs,

	.pfaf_mbox_intr_handler = otx2_pfaf_mbox_intr_handler,

};



void otx2_init_hw_ops(struct otx2_nic *pfvf)

{

	if (!test_bit(CN10K_LMTST, &pfvf->hw.cap_flag)) {

		pfvf->hw_ops = &otx2_hw_ops;

		return;

	}



	pfvf->hw_ops = &cn10k_hw_ops;

}

EXPORT_SYMBOL(otx2_init_hw_ops);



int cn10k_lmtst_init(struct otx2_nic *pfvf)

{
@@ -30,12 +43,9 @@ int cn10k_lmtst_init(struct otx2_nic *pfvf) 
	struct otx2_lmt_info *lmt_info;

	int err, cpu;



	if (!test_bit(CN10K_LMTST, &pfvf->hw.cap_flag)) {

		pfvf->hw_ops = &otx2_hw_ops;

	if (!test_bit(CN10K_LMTST, &pfvf->hw.cap_flag))

		return 0;

	}



	pfvf->hw_ops = &cn10k_hw_ops;

	/* Total LMTLINES = num_online_cpus() * 32 (For Burst flush).*/

	pfvf->tot_lmt_lines = (num_online_cpus() * LMT_BURST_SIZE);

	pfvf->hw.lmt_info = alloc_percpu(struct otx2_lmt_info);

drivers/net/ethernet/marvell/octeontx2/nic/cn10k.h

+1 −0
Original line number Diff line number Diff line
@@ -39,4 +39,5 @@ int cn10k_alloc_leaf_profile(struct otx2_nic *pfvf, u16 *leaf); 
int cn10k_set_ipolicer_rate(struct otx2_nic *pfvf, u16 profile,

			    u32 burst, u64 rate, bool pps);

int cn10k_free_leaf_profile(struct otx2_nic *pfvf, u16 leaf);

void otx2_init_hw_ops(struct otx2_nic *pfvf);

#endif /* CN10K_H */

drivers/net/ethernet/marvell/octeontx2/nic/cn20k.c

0 → 100644
+63 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/* Marvell RVU Ethernet driver

 *

 * Copyright (C) 2024 Marvell.

 *

 */



#include "otx2_common.h"

#include "otx2_reg.h"

#include "otx2_struct.h"

#include "cn10k.h"



static struct dev_hw_ops cn20k_hw_ops = {

	.pfaf_mbox_intr_handler = cn20k_pfaf_mbox_intr_handler,

};



void cn20k_init(struct otx2_nic *pfvf)

{

	pfvf->hw_ops = &cn20k_hw_ops;

}

EXPORT_SYMBOL(cn20k_init);

/* CN20K mbox AF => PFx irq handler */

irqreturn_t cn20k_pfaf_mbox_intr_handler(int irq, void *pf_irq)

{

	struct otx2_nic *pf = pf_irq;

	struct mbox *mw = &pf->mbox;

	struct otx2_mbox_dev *mdev;

	struct otx2_mbox *mbox;

	struct mbox_hdr *hdr;

	u64 pf_trig_val;



	pf_trig_val = otx2_read64(pf, RVU_PF_INT) & 0x3ULL;



	/* Clear the IRQ */

	otx2_write64(pf, RVU_PF_INT, pf_trig_val);



	if (pf_trig_val & BIT_ULL(0)) {

		mbox = &mw->mbox_up;

		mdev = &mbox->dev[0];

		otx2_sync_mbox_bbuf(mbox, 0);



		hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start);

		if (hdr->num_msgs)

			queue_work(pf->mbox_wq, &mw->mbox_up_wrk);



		trace_otx2_msg_interrupt(pf->pdev, "UP message from AF to PF",

					 BIT_ULL(0));

	}



	if (pf_trig_val & BIT_ULL(1)) {

		mbox = &mw->mbox;

		mdev = &mbox->dev[0];

		otx2_sync_mbox_bbuf(mbox, 0);



		hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start);

		if (hdr->num_msgs)

			queue_work(pf->mbox_wq, &mw->mbox_wrk);

		trace_otx2_msg_interrupt(pf->pdev, "DOWN reply from AF to PF",

					 BIT_ULL(1));

	}



	return IRQ_HANDLED;

}