Commit 3832dc42 authored by Cristian Ciocaltea's avatar Cristian Ciocaltea Committed by Heiko Stuebner
Browse files

dt-bindings: display: vop2: Add optional PLL clock property for rk3576 



As with the RK3588 SoC, RK3576 also allows the use of HDMI PHY PLL as an
alternative and more accurate pixel clock source for VOP2.

Document the optional PLL clock property.

Moreover, given that this is part of a series intended to address some
recent display problems, provide the appropriate tags to facilitate
backporting.

Fixes: c3b7c5a4 ("dt-bindings: display: vop2: Add rk3576 support")
Cc: stable@vger.kernel.org
Signed-off-by: default avatarCristian Ciocaltea <cristian.ciocaltea@collabora.com>
Reviewed-by: default avatar"Rob Herring (Arm)" <robh@kernel.org>
Tested-by: default avatarNicolas Frattaroli <nicolas.frattaroli@collabora.com>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20250612-rk3576-hdmitx-fix-v1-1-4b11007d8675@collabora.com
parent 8733bf4c

Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml

+44 −12
Original line number Diff line number Diff line
@@ -64,10 +64,10 @@ properties: 
      - description: Pixel clock for video port 0.

      - description: Pixel clock for video port 1.

      - description: Pixel clock for video port 2.

      - description: Pixel clock for video port 3.

      - description: Peripheral(vop grf/dsi) clock.

      - description: Alternative pixel clock provided by HDMI0 PHY PLL.

      - description: Alternative pixel clock provided by HDMI1 PHY PLL.

      - {}

      - {}

      - {}

      - {}



  clock-names:

    minItems: 5
@@ -77,10 +77,10 @@ properties: 
      - const: dclk_vp0

      - const: dclk_vp1

      - const: dclk_vp2

      - const: dclk_vp3

      - const: pclk_vop

      - const: pll_hdmiphy0

      - const: pll_hdmiphy1

      - {}

      - {}

      - {}

      - {}



  rockchip,grf:

    $ref: /schemas/types.yaml#/definitions/phandle
@@ -175,10 +175,24 @@ allOf: 
    then:

      properties:

        clocks:

          maxItems: 5

          minItems: 5

          items:

            - {}

            - {}

            - {}

            - {}

            - {}

            - description: Alternative pixel clock provided by HDMI PHY PLL.



        clock-names:

          maxItems: 5

          minItems: 5

          items:

            - {}

            - {}

            - {}

            - {}

            - {}

            - const: pll_hdmiphy0



        interrupts:

          minItems: 4
@@ -208,11 +222,29 @@ allOf: 
      properties:

        clocks:

          minItems: 7

          maxItems: 9

          items:

            - {}

            - {}

            - {}

            - {}

            - {}

            - description: Pixel clock for video port 3.

            - description: Peripheral(vop grf/dsi) clock.

            - description: Alternative pixel clock provided by HDMI0 PHY PLL.

            - description: Alternative pixel clock provided by HDMI1 PHY PLL.



        clock-names:

          minItems: 7

          maxItems: 9

          items:

            - {}

            - {}

            - {}

            - {}

            - {}

            - const: dclk_vp3

            - const: pclk_vop

            - const: pll_hdmiphy0

            - const: pll_hdmiphy1



        interrupts:

          maxItems: 1