Commit 386a1832 authored by Suraj Kandpal's avatar Suraj Kandpal
Browse files

drm/i915/dpll: Rename intel_shared_dpll 



Rename intel_shared_dpll to intel_dpll to represent both
shared and individual dplls. Since from MTL each PHY has it's
own PLL making the shared PLL naming a little outdated. In an
effort to make this framework accepting of future changes this
needs to be done.

--v2
-Use intel_dpll_global to make sure names start with the filename
[Jani/Ville]
-Explain the need of this rename [Jani]

--v3
-Just keep it intel_dpll [Jani]

--v4
-Fix comment [Jani]
-Use just num_dpll and dplls [Jani]

Signed-off-by: default avatarSuraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://lore.kernel.org/r/20250515071801.2221120-7-suraj.kandpal@intel.com
parent 6cc235f7

drivers/gpu/drm/i915/display/icl_dsi.c

+1 −1
Original line number Diff line number Diff line
@@ -658,7 +658,7 @@ static void gen11_dsi_map_pll(struct intel_encoder *encoder, 
{

	struct intel_display *display = to_intel_display(encoder);

	struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);

	struct intel_shared_dpll *pll = crtc_state->shared_dpll;

	struct intel_dpll *pll = crtc_state->intel_dpll;

	enum phy phy;

	u32 val;

drivers/gpu/drm/i915/display/intel_ddi.c

+26 −26
Original line number Diff line number Diff line
@@ -236,7 +236,7 @@ static void intel_wait_ddi_buf_active(struct intel_encoder *encoder) 
			port_name(port));

}



static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll)

static u32 hsw_pll_to_ddi_pll_sel(const struct intel_dpll *pll)

{

	switch (pll->info->id) {

	case DPLL_ID_WRPLL1:
@@ -260,7 +260,7 @@ static u32 hsw_pll_to_ddi_pll_sel(const struct intel_shared_dpll *pll) 
static u32 icl_pll_to_ddi_clk_sel(struct intel_encoder *encoder,

				  const struct intel_crtc_state *crtc_state)

{

	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;

	const struct intel_dpll *pll = crtc_state->intel_dpll;

	int clock = crtc_state->port_clock;

	const enum intel_dpll_id id = pll->info->id;
@@ -1561,7 +1561,7 @@ static bool _icl_ddi_is_clock_enabled(struct intel_display *display, i915_reg_t 
	return !(intel_de_read(display, reg) & clk_off);

}



static struct intel_shared_dpll *

static struct intel_dpll *

_icl_ddi_get_pll(struct intel_display *display, i915_reg_t reg,

		 u32 clk_sel_mask, u32 clk_sel_shift)

{
@@ -1576,7 +1576,7 @@ static void adls_ddi_enable_clock(struct intel_encoder *encoder, 
				  const struct intel_crtc_state *crtc_state)

{

	struct intel_display *display = to_intel_display(encoder);

	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;

	const struct intel_dpll *pll = crtc_state->intel_dpll;

	enum phy phy = intel_encoder_to_phy(encoder);



	if (drm_WARN_ON(display->drm, !pll))
@@ -1606,7 +1606,7 @@ static bool adls_ddi_is_clock_enabled(struct intel_encoder *encoder) 
					 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));

}



static struct intel_shared_dpll *adls_ddi_get_pll(struct intel_encoder *encoder)

static struct intel_dpll *adls_ddi_get_pll(struct intel_encoder *encoder)

{

	struct intel_display *display = to_intel_display(encoder);

	enum phy phy = intel_encoder_to_phy(encoder);
@@ -1620,7 +1620,7 @@ static void rkl_ddi_enable_clock(struct intel_encoder *encoder, 
				 const struct intel_crtc_state *crtc_state)

{

	struct intel_display *display = to_intel_display(encoder);

	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;

	const struct intel_dpll *pll = crtc_state->intel_dpll;

	enum phy phy = intel_encoder_to_phy(encoder);



	if (drm_WARN_ON(display->drm, !pll))
@@ -1650,7 +1650,7 @@ static bool rkl_ddi_is_clock_enabled(struct intel_encoder *encoder) 
					 RKL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));

}



static struct intel_shared_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder)

static struct intel_dpll *rkl_ddi_get_pll(struct intel_encoder *encoder)

{

	struct intel_display *display = to_intel_display(encoder);

	enum phy phy = intel_encoder_to_phy(encoder);
@@ -1664,7 +1664,7 @@ static void dg1_ddi_enable_clock(struct intel_encoder *encoder, 
				 const struct intel_crtc_state *crtc_state)

{

	struct intel_display *display = to_intel_display(encoder);

	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;

	const struct intel_dpll *pll = crtc_state->intel_dpll;

	enum phy phy = intel_encoder_to_phy(encoder);



	if (drm_WARN_ON(display->drm, !pll))
@@ -1703,7 +1703,7 @@ static bool dg1_ddi_is_clock_enabled(struct intel_encoder *encoder) 
					 DG1_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));

}



static struct intel_shared_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder)

static struct intel_dpll *dg1_ddi_get_pll(struct intel_encoder *encoder)

{

	struct intel_display *display = to_intel_display(encoder);

	enum phy phy = intel_encoder_to_phy(encoder);
@@ -1730,7 +1730,7 @@ static void icl_ddi_combo_enable_clock(struct intel_encoder *encoder, 
				       const struct intel_crtc_state *crtc_state)

{

	struct intel_display *display = to_intel_display(encoder);

	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;

	const struct intel_dpll *pll = crtc_state->intel_dpll;

	enum phy phy = intel_encoder_to_phy(encoder);



	if (drm_WARN_ON(display->drm, !pll))
@@ -1760,7 +1760,7 @@ static bool icl_ddi_combo_is_clock_enabled(struct intel_encoder *encoder) 
					 ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy));

}



struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder)

struct intel_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder)

{

	struct intel_display *display = to_intel_display(encoder);

	enum phy phy = intel_encoder_to_phy(encoder);
@@ -1774,7 +1774,7 @@ static void jsl_ddi_tc_enable_clock(struct intel_encoder *encoder, 
				    const struct intel_crtc_state *crtc_state)

{

	struct intel_display *display = to_intel_display(encoder);

	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;

	const struct intel_dpll *pll = crtc_state->intel_dpll;

	enum port port = encoder->port;



	if (drm_WARN_ON(display->drm, !pll))
@@ -1817,7 +1817,7 @@ static void icl_ddi_tc_enable_clock(struct intel_encoder *encoder, 
				    const struct intel_crtc_state *crtc_state)

{

	struct intel_display *display = to_intel_display(encoder);

	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;

	const struct intel_dpll *pll = crtc_state->intel_dpll;

	enum tc_port tc_port = intel_encoder_to_tc(encoder);

	enum port port = encoder->port;
@@ -1868,7 +1868,7 @@ static bool icl_ddi_tc_is_clock_enabled(struct intel_encoder *encoder) 
	return !(tmp & ICL_DPCLKA_CFGCR0_TC_CLK_OFF(tc_port));

}



static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder)

static struct intel_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encoder)

{

	struct intel_display *display = to_intel_display(encoder);

	enum tc_port tc_port = intel_encoder_to_tc(encoder);
@@ -1898,7 +1898,7 @@ static struct intel_shared_dpll *icl_ddi_tc_get_pll(struct intel_encoder *encode 
	return intel_get_shared_dpll_by_id(display, id);

}



static struct intel_shared_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder)

static struct intel_dpll *bxt_ddi_get_pll(struct intel_encoder *encoder)

{

	struct intel_display *display = to_intel_display(encoder->base.dev);

	enum intel_dpll_id id;
@@ -1925,7 +1925,7 @@ static void skl_ddi_enable_clock(struct intel_encoder *encoder, 
				 const struct intel_crtc_state *crtc_state)

{

	struct intel_display *display = to_intel_display(encoder);

	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;

	const struct intel_dpll *pll = crtc_state->intel_dpll;

	enum port port = encoder->port;



	if (drm_WARN_ON(display->drm, !pll))
@@ -1967,7 +1967,7 @@ static bool skl_ddi_is_clock_enabled(struct intel_encoder *encoder) 
	return !(intel_de_read(display, DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_OFF(port));

}



static struct intel_shared_dpll *skl_ddi_get_pll(struct intel_encoder *encoder)

static struct intel_dpll *skl_ddi_get_pll(struct intel_encoder *encoder)

{

	struct intel_display *display = to_intel_display(encoder);

	enum port port = encoder->port;
@@ -1993,7 +1993,7 @@ void hsw_ddi_enable_clock(struct intel_encoder *encoder, 
			  const struct intel_crtc_state *crtc_state)

{

	struct intel_display *display = to_intel_display(encoder);

	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;

	const struct intel_dpll *pll = crtc_state->intel_dpll;

	enum port port = encoder->port;



	if (drm_WARN_ON(display->drm, !pll))
@@ -2018,7 +2018,7 @@ bool hsw_ddi_is_clock_enabled(struct intel_encoder *encoder) 
	return intel_de_read(display, PORT_CLK_SEL(port)) != PORT_CLK_SEL_NONE;

}



static struct intel_shared_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder)

static struct intel_dpll *hsw_ddi_get_pll(struct intel_encoder *encoder)

{

	struct intel_display *display = to_intel_display(encoder);

	enum port port = encoder->port;
@@ -4187,7 +4187,7 @@ static void intel_ddi_get_config(struct intel_encoder *encoder, 


void intel_ddi_get_clock(struct intel_encoder *encoder,

			 struct intel_crtc_state *crtc_state,

			 struct intel_shared_dpll *pll)

			 struct intel_dpll *pll)

{

	struct intel_display *display = to_intel_display(encoder);

	enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT;
@@ -4203,7 +4203,7 @@ void intel_ddi_get_clock(struct intel_encoder *encoder, 


	icl_set_active_port_dpll(crtc_state, port_dpll_id);



	crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->shared_dpll,

	crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->intel_dpll,

						     &crtc_state->dpll_hw_state);

}
@@ -4257,7 +4257,7 @@ static void icl_ddi_combo_get_config(struct intel_encoder *encoder, 
	intel_ddi_get_config(encoder, crtc_state);

}



static bool icl_ddi_tc_pll_is_tbt(const struct intel_shared_dpll *pll)

static bool icl_ddi_tc_pll_is_tbt(const struct intel_dpll *pll)

{

	return pll->info->id == DPLL_ID_ICL_TBTPLL;

}
@@ -4267,7 +4267,7 @@ icl_ddi_tc_port_pll_type(struct intel_encoder *encoder, 
			 const struct intel_crtc_state *crtc_state)

{

	struct intel_display *display = to_intel_display(encoder);

	const struct intel_shared_dpll *pll = crtc_state->shared_dpll;

	const struct intel_dpll *pll = crtc_state->intel_dpll;



	if (drm_WARN_ON(display->drm, !pll))

		return ICL_PORT_DPLL_DEFAULT;
@@ -4290,7 +4290,7 @@ intel_ddi_port_pll_type(struct intel_encoder *encoder, 


static void icl_ddi_tc_get_clock(struct intel_encoder *encoder,

				 struct intel_crtc_state *crtc_state,

				 struct intel_shared_dpll *pll)

				 struct intel_dpll *pll)

{

	struct intel_display *display = to_intel_display(encoder);

	enum icl_port_dpll_id port_dpll_id;
@@ -4313,10 +4313,10 @@ static void icl_ddi_tc_get_clock(struct intel_encoder *encoder, 


	icl_set_active_port_dpll(crtc_state, port_dpll_id);



	if (icl_ddi_tc_pll_is_tbt(crtc_state->shared_dpll))

	if (icl_ddi_tc_pll_is_tbt(crtc_state->intel_dpll))

		crtc_state->port_clock = icl_calc_tbt_pll_link(display, encoder->port);

	else

		crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->shared_dpll,

		crtc_state->port_clock = intel_dpll_get_freq(display, crtc_state->intel_dpll,

							     &crtc_state->dpll_hw_state);

}

drivers/gpu/drm/i915/display/intel_ddi.h

+3 −3
Original line number Diff line number Diff line
@@ -16,9 +16,9 @@ struct intel_crtc; 
struct intel_crtc_state;

struct intel_display;

struct intel_dp;

struct intel_dpll;

struct intel_dpll_hw_state;

struct intel_encoder;

struct intel_shared_dpll;

enum pipe;

enum port;

enum transcoder;
@@ -40,7 +40,7 @@ void intel_ddi_enable_clock(struct intel_encoder *encoder, 
void intel_ddi_disable_clock(struct intel_encoder *encoder);

void intel_ddi_get_clock(struct intel_encoder *encoder,

			 struct intel_crtc_state *crtc_state,

			 struct intel_shared_dpll *pll);

			 struct intel_dpll *pll);

void hsw_ddi_enable_clock(struct intel_encoder *encoder,

			  const struct intel_crtc_state *crtc_state);

void hsw_ddi_disable_clock(struct intel_encoder *encoder);
@@ -50,7 +50,7 @@ intel_ddi_port_pll_type(struct intel_encoder *encoder, 
			const struct intel_crtc_state *crtc_state);

void hsw_ddi_get_config(struct intel_encoder *encoder,

			struct intel_crtc_state *crtc_state);

struct intel_shared_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder);

struct intel_dpll *icl_ddi_combo_get_pll(struct intel_encoder *encoder);

void hsw_prepare_dp_ddi_buffers(struct intel_encoder *encoder,

				const struct intel_crtc_state *crtc_state);

void intel_wait_ddi_buf_idle(struct intel_display *display, enum port port);

drivers/gpu/drm/i915/display/intel_display.c

+6 −6
Original line number Diff line number Diff line
@@ -1325,7 +1325,7 @@ static void intel_encoders_update_prepare(struct intel_atomic_state *state) 
			if (intel_crtc_needs_modeset(new_crtc_state))

				continue;



			new_crtc_state->shared_dpll = old_crtc_state->shared_dpll;

			new_crtc_state->intel_dpll = old_crtc_state->intel_dpll;

			new_crtc_state->dpll_hw_state = old_crtc_state->dpll_hw_state;

		}

	}
@@ -1663,7 +1663,7 @@ static void hsw_crtc_enable(struct intel_atomic_state *state, 


	intel_encoders_pre_pll_enable(state, crtc);



	if (new_crtc_state->shared_dpll)

	if (new_crtc_state->intel_dpll)

		intel_enable_shared_dpll(new_crtc_state);



	intel_encoders_pre_enable(state, crtc);
@@ -1959,7 +1959,7 @@ static void get_crtc_power_domains(struct intel_crtc_state *crtc_state, 
	if (HAS_DDI(display) && crtc_state->has_audio)

		set_bit(POWER_DOMAIN_AUDIO_MMIO, mask->bits);



	if (crtc_state->shared_dpll)

	if (crtc_state->intel_dpll)

		set_bit(POWER_DOMAIN_DISPLAY_CORE, mask->bits);



	if (crtc_state->dsc.compression_enable)
@@ -4509,7 +4509,7 @@ copy_joiner_crtc_state_modeset(struct intel_atomic_state *state, 
	/* preserve some things from the slave's original crtc state */

	saved_state->uapi = secondary_crtc_state->uapi;

	saved_state->scaler_state = secondary_crtc_state->scaler_state;

	saved_state->shared_dpll = secondary_crtc_state->shared_dpll;

	saved_state->intel_dpll = secondary_crtc_state->intel_dpll;

	saved_state->crc_enabled = secondary_crtc_state->crc_enabled;



	intel_crtc_free_hw_state(secondary_crtc_state);
@@ -4572,7 +4572,7 @@ intel_crtc_prepare_cleared_state(struct intel_atomic_state *state, 
	saved_state->uapi = crtc_state->uapi;

	saved_state->inherited = crtc_state->inherited;

	saved_state->scaler_state = crtc_state->scaler_state;

	saved_state->shared_dpll = crtc_state->shared_dpll;

	saved_state->intel_dpll = crtc_state->intel_dpll;

	saved_state->dpll_hw_state = crtc_state->dpll_hw_state;

	memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls,

	       sizeof(saved_state->icl_port_dplls));
@@ -5326,7 +5326,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, 
	PIPE_CONF_CHECK_BOOL(double_wide);



	if (display->dpll.mgr)

		PIPE_CONF_CHECK_P(shared_dpll);

		PIPE_CONF_CHECK_P(intel_dpll);



	/* FIXME convert everything over the dpll_mgr */

	if (display->dpll.mgr || HAS_GMCH(display))

drivers/gpu/drm/i915/display/intel_display_core.h

+2 −2
Original line number Diff line number Diff line
@@ -125,8 +125,8 @@ struct intel_audio { 
struct intel_dpll_global {

	struct mutex lock;



	int num_shared_dpll;

	struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];

	int num_dpll;

	struct intel_dpll dplls[I915_NUM_PLLS];

	const struct intel_dpll_mgr *mgr;



	struct {