Commit 39db0e13 authored by Anson Huang's avatar Anson Huang Committed by Shawn Guo
Browse files

ARM: dts: imx6: add mmdc ipg clock 



i.MX6 SoCs has MMDC clock gates in CCM CCGR, add
clock property for MMDC driver's clock operation.

Signed-off-by: default avatarAnson Huang <Anson.Huang@nxp.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 46f3b54d

arch/arm/boot/dts/imx6qdl.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -1115,6 +1115,7 @@ romcp@21ac000 { 
			mmdc0: mmdc@21b0000 { /* MMDC0 */

				compatible = "fsl,imx6q-mmdc";

				reg = <0x021b0000 0x4000>;

				clocks = <&clks IMX6QDL_CLK_MMDC_P0_IPG>;

			};



			mmdc1: mmdc@21b4000 { /* MMDC1 */

arch/arm/boot/dts/imx6sl.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -921,6 +921,7 @@ i2c3: i2c@21a8000 { 
			mmdc: mmdc@21b0000 {

				compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc";

				reg = <0x021b0000 0x4000>;

				clocks = <&clks IMX6SL_CLK_MMDC_P0_IPG>;

			};



			rngb: rngb@21b4000 {

arch/arm/boot/dts/imx6sll.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -770,6 +770,7 @@ i2c3: i2c@21a8000 { 
			mmdc: memory-controller@21b0000 {

				compatible = "fsl,imx6sll-mmdc", "fsl,imx6q-mmdc";

				reg = <0x021b0000 0x4000>;

				clocks = <&clks IMX6SLL_CLK_MMDC_P0_IPG>;

			};



			ocotp: ocotp-ctrl@21bc000 {

arch/arm/boot/dts/imx6sx.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -1002,6 +1002,7 @@ i2c3: i2c@21a8000 { 
			mmdc: mmdc@21b0000 {

				compatible = "fsl,imx6sx-mmdc", "fsl,imx6q-mmdc";

				reg = <0x021b0000 0x4000>;

				clocks = <&clks IMX6SX_CLK_MMDC_P0_IPG>;

			};



			fec2: ethernet@21b4000 {

arch/arm/boot/dts/imx6ul.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -917,6 +917,7 @@ i2c3: i2c@21a8000 { 
			mmdc: mmdc@21b0000 {

				compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";

				reg = <0x021b0000 0x4000>;

				clocks = <&clks IMX6UL_CLK_MMDC_P0_IPG>;

			};



			weim: weim@21b8000 {