Commit 3a088b07 authored by Zhang Rui's avatar Zhang Rui Committed by Len Brown
Browse files

tools/power turbostat: Fix DMR support 



Together with the RAPL MSRs, there are more MSRs gone on DMR, including
PLR (Perf Limit Reasons), and IRTL (Package cstate Interrupt Response
Time Limit) MSRs. The configurable TDP info should also be retrieved
from TPMI based Intel Speed Select Technology feature.

Remove the access of these MSRs for DMR. Improve the DMR platform
feature table to make it more readable at the same time.

Fixes: 83075bd5 ("tools/power turbostat: Add initial support for DMR")
Signed-off-by: default avatarZhang Rui <rui.zhang@intel.com>
Signed-off-by: default avatarLen Brown <len.brown@intel.com>
parent dcd1c379

tools/power/x86/turbostat/turbostat.c

+15 −14
Original line number Diff line number Diff line
@@ -992,17 +992,18 @@ static const struct platform_features dmr_features = { 
	.has_msr_misc_feature_control	= spr_features.has_msr_misc_feature_control,

	.has_msr_misc_pwr_mgmt		= spr_features.has_msr_misc_pwr_mgmt,

	.has_nhm_msrs			= spr_features.has_nhm_msrs,

	.has_config_tdp = spr_features.has_config_tdp,

	.bclk_freq			= spr_features.bclk_freq,

	.supported_cstates		= spr_features.supported_cstates,

	.cst_limit			= spr_features.cst_limit,

	.has_msr_core_c1_res		= spr_features.has_msr_core_c1_res,

	.has_msr_module_c6_res_ms = 1,	/* DMR has Dual Core Module and MC6 MSR */

	.has_irtl_msrs = spr_features.has_irtl_msrs,

	.has_cst_prewake_bit		= spr_features.has_cst_prewake_bit,

	.has_fixed_rapl_psys_unit	= spr_features.has_fixed_rapl_psys_unit,

	.trl_msrs			= spr_features.trl_msrs,

	.has_msr_module_c6_res_ms	= 1,	/* DMR has Dual-Core-Module and MC6 MSR */

	.rapl_msrs			= 0,	/* DMR does not have RAPL MSRs */

	.plr_msrs			= 0,	/* DMR does not have PLR  MSRs */

	.has_irtl_msrs			= 0,	/* DMR does not have IRTL MSRs */

	.has_config_tdp			= 0,	/* DMR does not have CTDP MSRs */

};



static const struct platform_features srf_features = {