Unverified Commit 3aae991c authored by Stephen Boyd's avatar Stephen Boyd
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Merge branches 'clk-samsung', 'clk-tegra' and 'clk-amlogic' into clk-next 

* clk-samsung:
  clk: s2mps11: add support for S2MPG10 PMIC clock
  dt-bindings: clock: samsung,s2mps11: add s2mpg10
  clk: samsung: exynos990: Add PERIC0 and PERIC1 clock support
  dt-bindings: clock: exynos990: Add PERIC0 and PERIC1 clock units
  clk: samsung: exynos990: Add missing USB clock registers to HSI0
  clk: samsung: exynos990: Add LHS_ACEL gate clock for HSI0 and update CLK_NR_TOP
  dt-bindings: clock: exynos990: Add LHS_ACEL clock ID for HSI0 block
  clk: samsung: artpec-8: Add initial clock support for ARTPEC-8 SoC
  clk: samsung: Add clock PLL support for ARTPEC-8 SoC
  dt-bindings: clock: Add ARTPEC-8 clock controller
  clk: samsung: exynos990: Add DPU_BUS and CMUREF mux/div and update CLKS_NR_TOP
  dt-bindings: clock: exynos990: Extend clocks IDs
  clk: samsung: exynos990: Replace bogus divs with fixed-factor clocks
  clk: samsung: exynos990: Fix CMU_TOP mux/div bit widths
  clk: samsung: exynos990: Use PLL_CON0 for PLL parent muxes
  clk: samsung: pll: convert from round_rate() to determine_rate()
  clk: samsung: cpu: convert from round_rate() to determine_rate()
  clk: samsung: fsd: Add clk id for PCLK and PLL in CAM_CSI block
  dt-bindings: clock: Add CAM_CSI clock macro for FSD

* clk-tegra:
  clk: tegra: dfll: Add CVB tables for Tegra114
  clk: tegra: Add DFLL DVCO reset control for Tegra114
  dt-bindings: arm: tegra: Add ASUS TF101G and SL101
  dt-bindings: reset: Add Tegra114 CAR header
  dt-bindings: arm: tegra: Add Xiaomi Mi Pad (A0101)
  dt-bindings: clock: tegra30: Add IDs for CSI pad clocks
  dt-bindings: display: tegra: Move avdd-dsi-csi-supply from VI to CSI
  dt-bindings: i2c: nvidia,tegra20-i2c: Document Tegra264 I2C

* clk-amlogic:
  clk: amlogic: fix recent code refactoring
  clk: amlogic: c3-peripherals: use helper for basic composite clocks
  clk: amlogic: align s4 and c3 pwm clock descriptions
  clk: amlogic: add composite clock helpers
  clk: amlogic: use the common pclk definition
  clk: amlogic: introduce a common pclk definition
  clk: amlogic: pclk explicitly use CLK_IGNORE_UNUSED
  clk: amlogic: drop CLK_SET_RATE_PARENT from peripheral clocks
  clk: amlogic: move PCLK definition to clkc-utils
  clk: amlogic: aoclk: use clkc-utils syscon probe
  clk: amlogic: use probe helper in mmio based controllers
  clk: amlogic: add probe helper for mmio based controllers
  clk: amlogic: drop meson-clkcee
  clk: amlogic: naming consistency alignment
parents ec733647 823699cc ccd74bec 7e2e4e32

Documentation/devicetree/bindings/arm/tegra.yaml

+10 −2
Original line number Diff line number Diff line
@@ -36,8 +36,12 @@ properties: 
              - toradex,colibri_t20-iris

          - const: toradex,colibri_t20

          - const: nvidia,tegra20

      - items:

          - const: asus,tf101

      - description: ASUS Transformers T20 Device family

        items:

          - enum:

              - asus,sl101

              - asus,tf101

              - asus,tf101g

          - const: nvidia,tegra20

      - items:

          - const: acer,picasso
@@ -174,6 +178,10 @@ properties: 
          - const: google,nyan-big

          - const: google,nyan

          - const: nvidia,tegra124

      - description: Xiaomi Mi Pad (A0101)

        items:

          - const: xiaomi,mocha

          - const: nvidia,tegra124

      - items:

          - enum:

              - nvidia,darcy

Documentation/devicetree/bindings/clock/axis,artpec8-clock.yaml

0 → 100644
+213 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/axis,artpec8-clock.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Axis ARTPEC-8 SoC clock controller



maintainers:

  - Jesper Nilsson <jesper.nilsson@axis.com>



description: |

  ARTPEC-8 clock controller is comprised of several CMU (Clock Management Unit)

  units, generating clocks for different domains. Those CMU units are modeled

  as separate device tree nodes, and might depend on each other.

  The root clock in that root tree is an external clock: OSCCLK (25 MHz).

  This external clock must be defined as a fixed-rate clock in dts.



  CMU_CMU is a top-level CMU, where all base clocks are prepared using PLLs and

  dividers; all other clocks of function blocks (other CMUs) are usually

  derived from CMU_CMU.



  Each clock is assigned an identifier and client nodes can use this identifier

  to specify the clock which they consume. All clocks available for usage

  in clock consumer nodes are defined as preprocessor macros in

  'include/dt-bindings/clock/axis,artpec8-clk.h' header.



properties:

  compatible:

    enum:

      - axis,artpec8-cmu-cmu

      - axis,artpec8-cmu-bus

      - axis,artpec8-cmu-core

      - axis,artpec8-cmu-cpucl

      - axis,artpec8-cmu-fsys

      - axis,artpec8-cmu-imem

      - axis,artpec8-cmu-peri



  reg:

    maxItems: 1



  clocks:

    minItems: 1

    maxItems: 5



  clock-names:

    minItems: 1

    maxItems: 5



  "#clock-cells":

    const: 1



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - "#clock-cells"



allOf:

  - if:

      properties:

        compatible:

          const: axis,artpec8-cmu-cmu



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (25 MHz)



        clock-names:

          items:

            - const: fin_pll



  - if:

      properties:

        compatible:

          const: axis,artpec8-cmu-bus



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (25 MHz)

            - description: CMU_BUS BUS clock (from CMU_CMU)

            - description: CMU_BUS DLP clock (from CMU_CMU)



        clock-names:

          items:

            - const: fin_pll

            - const: bus

            - const: dlp



  - if:

      properties:

        compatible:

          const: axis,artpec8-cmu-core



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (25 MHz)

            - description: CMU_CORE main clock (from CMU_CMU)

            - description: CMU_CORE DLP clock (from CMU_CMU)



        clock-names:

          items:

            - const: fin_pll

            - const: main

            - const: dlp



  - if:

      properties:

        compatible:

          const: axis,artpec8-cmu-cpucl



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (25 MHz)

            - description: CMU_CPUCL switch clock (from CMU_CMU)



        clock-names:

          items:

            - const: fin_pll

            - const: switch



  - if:

      properties:

        compatible:

          const: axis,artpec8-cmu-fsys



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (25 MHz)

            - description: CMU_FSYS SCAN0 clock (from CMU_CMU)

            - description: CMU_FSYS SCAN1 clock (from CMU_CMU)

            - description: CMU_FSYS BUS clock (from CMU_CMU)

            - description: CMU_FSYS IP clock (from CMU_CMU)



        clock-names:

          items:

            - const: fin_pll

            - const: scan0

            - const: scan1

            - const: bus

            - const: ip



  - if:

      properties:

        compatible:

          const: axis,artpec8-cmu-imem



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (25 MHz)

            - description: CMU_IMEM ACLK clock (from CMU_CMU)

            - description: CMU_IMEM JPEG clock (from CMU_CMU)



        clock-names:

          items:

            - const: fin_pll

            - const: aclk

            - const: jpeg



  - if:

      properties:

        compatible:

          const: axis,artpec8-cmu-peri



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (25 MHz)

            - description: CMU_PERI IP clock (from CMU_CMU)

            - description: CMU_PERI AUDIO clock (from CMU_CMU)

            - description: CMU_PERI DISP clock (from CMU_CMU)



        clock-names:

          items:

            - const: fin_pll

            - const: ip

            - const: audio

            - const: disp



additionalProperties: false



examples:

  # Clock controller node for CMU_FSYS

  - |

    #include <dt-bindings/clock/axis,artpec8-clk.h>



    cmu_fsys: clock-controller@16c10000 {

        compatible = "axis,artpec8-cmu-fsys";

        reg = <0x16c10000 0x4000>;

        #clock-cells = <1>;

        clocks = <&fin_pll>,

                 <&cmu_cmu CLK_DOUT_CMU_FSYS_SCAN0>,

                 <&cmu_cmu CLK_DOUT_CMU_FSYS_SCAN1>,

                 <&cmu_cmu CLK_DOUT_CMU_FSYS_BUS>,

                 <&cmu_cmu CLK_DOUT_CMU_FSYS_IP>;

        clock-names = "fin_pll", "scan0", "scan1", "bus", "ip";

    };



...

Documentation/devicetree/bindings/clock/samsung,exynos990-clock.yaml

+24 −0
Original line number Diff line number Diff line
@@ -30,6 +30,8 @@ description: | 
properties:

  compatible:

    enum:

      - samsung,exynos990-cmu-peric1

      - samsung,exynos990-cmu-peric0

      - samsung,exynos990-cmu-hsi0

      - samsung,exynos990-cmu-peris

      - samsung,exynos990-cmu-top
@@ -56,6 +58,28 @@ required: 
  - reg



allOf:

  - if:

      properties:

        compatible:

          contains:

            enum:

              - samsung,exynos990-cmu-peric1

              - samsung,exynos990-cmu-peric0



    then:

      properties:

        clocks:

          items:

            - description: External reference clock (26 MHz)

            - description: Connectivity Peripheral 0/1 bus clock (from CMU_TOP)

            - description: Connectivity Peripheral 0/1 IP clock (from CMU_TOP)



        clock-names:

          items:

            - const: oscclk

            - const: bus

            - const: ip



  - if:

      properties:

        compatible:

Documentation/devicetree/bindings/clock/samsung,s2mps11.yaml

+1 −0
Original line number Diff line number Diff line
@@ -25,6 +25,7 @@ description: | 
properties:

  compatible:

    enum:

      - samsung,s2mpg10-clk

      - samsung,s2mps11-clk

      - samsung,s2mps13-clk # S2MPS13 and S2MPS15

      - samsung,s2mps14-clk

Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vi.yaml

+0 −3
Original line number Diff line number Diff line
@@ -70,9 +70,6 @@ properties: 
  ranges:

    maxItems: 1



  avdd-dsi-csi-supply:

    description: DSI/CSI power supply. Must supply 1.2 V.



  vip:

    $ref: /schemas/display/tegra/nvidia,tegra20-vip.yaml