Commit 3b9ea5b5 authored by Linus Torvalds's avatar Linus Torvalds
Browse files
Pull devicetree updates from Rob Herring:
 "DT core:

   - Fix ref counting errors in interrupt parsing code

   - Allow "nonposted-mmio" property per device and on non-Apple h/w

   - Use typed accessors in platform driver code

   - Fix mismatch between DT MAX_PHANDLE_ARGS and
     NR_FWNODE_REFERENCE_ARGS and increase the maximum number args

   - Rework of_resolve_phandles() to use __free() cleanup and fix ref
     count error

   - Use of_prop_cmp() in a few more places

   - Improve make_fit.py script error handling

  DT bindings:

   - Update DT property ordering rules for properties within groups
     (i.e. common suffix)

   - Update DT submitting-patches doc to cover sending .dts patches and
     SoC maintainer rules on being warning free against linux-next

   - Add ti,tps53681, ti,tps53681, Maxim max15301, max15303, and
     max20751 to trivial devices

   - Add Renesas RZ/V2H(P) and Allwinner H616 support to Arm Mali
     Bifrost GPU. Add Samsung exynos7870 support to Arm Mail Midgard.

   - Rework qcom,ebi2 and samsung,exynos4210-sram memory controller
     bindings to split child node properties. Fix the LAN9115 binding to
     use the child node schema so all properties are documented.

   - Convert nxp,lpc3220-mic and Altera ECC manager bindings to schema

   - Fix some issues with LVDS display panels causing validation
     warnings

   - Drop some obsolete parts of Xilinx bindings"

* tag 'devicetree-for-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (48 commits)
  scripts/make_fit: Print DT name before libfdt errors
  dt-bindings: edac: altera: socfpga: Convert to YAML
  dt-bindings: pps: gpio: Correct indentation and style in DTS example
  media: dt-bindings: mediatek,vcodec-encoder: Drop assigned-clock properties
  of: address: Allow to specify nonposted-mmio per-device
  of: address: Expand nonposted-mmio to non-Apple Silicon platforms
  docs: dt-bindings: Specify ordering for properties within groups
  dt-bindings: gpu: arm,mali-midgard: add exynos7870-mali compatible
  of: Move of_prop_val_eq() next to the single user
  of/platform: Use typed accessors rather than of_get_property()
  dt-bindings: trivial-devices: Add Maxim max15301, max15303, and max20751
  dt-bindings: fsi: ibm,p9-scom: Add "ibm,fsi2pib" compatible
  dt-bindings: memory-controllers: qcom,ebi2: Enforce child props
  dt-bindings: memory-controllers: samsung,exynos4210-srom: Enforce child props
  dt-bindings: display: mitsubishi,aa104xd12: Adjust allowed and required properties
  dt-bindings: display: mitsubishi,aa104xd12: Allow jeida-18 for data-mapping
  dt-bindings: interrupt-controller: Convert nxp,lpc3220-mic.txt to yaml format
  docs: process: maintainer-soc-clean-dts: linux-next is decisive
  docs: dt: submitting-patches: Document sending DTS patches
  of: Align macro MAX_PHANDLE_ARGS with NR_FWNODE_REFERENCE_ARGS
  ...
parents 092e3350 314655d4
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Original line number Diff line number Diff line
@@ -41,6 +41,7 @@ properties:
          - enum:
              - ti,ds90cf364a # For the DS90CF364A FPD-Link LVDS Receiver
              - ti,ds90cf384a # For the DS90CF384A FPD-Link LVDS Receiver
              - ti,sn65lvds822  # For the SN65LVDS822 FlatLink LVDS Receiver
              - ti,sn65lvds94 # For the SN65DS94 LVDS serdes
          - const: lvds-decoder # Generic LVDS decoders compatible fallback
      - enum:
+4 −2
Original line number Diff line number Diff line
@@ -33,7 +33,9 @@ properties:
    description: Reference to the regulator powering the panel VCC pins.

  data-mapping:
    const: jeida-24
    enum:
      - jeida-18
      - jeida-24

  width-mm:
    const: 210
@@ -41,6 +43,7 @@ properties:
  height-mm:
    const: 158

  backlight: true
  panel-timing: true
  port: true

@@ -48,7 +51,6 @@ additionalProperties: false

required:
  - compatible
  - vcc-supply
  - data-mapping
  - width-mm
  - height-mm
+7 −1
Original line number Diff line number Diff line
@@ -133,6 +133,9 @@ The above-described ordering follows this approach:
3. Status is the last information to annotate that device node is or is not
   finished (board resources are needed).

The individual properties inside each group shall use natural sort order by
the property name.

Example::

	/* SoC DTSI */
@@ -158,7 +161,10 @@ Example::
	/* Board DTS */

	&device_node {
		vdd-supply = <&board_vreg1>;
		vdd-0v9-supply = <&board_vreg1>;
		vdd-1v8-supply = <&board_vreg4>;
		vdd-3v3-supply = <&board_vreg2>;
		vdd-12v-supply = <&board_vreg3>;
		status = "okay";
	}

+323 −0
Original line number Diff line number Diff line
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
# Copyright (C) 2025 Altera Corporation
%YAML 1.2
---
$id: http://devicetree.org/schemas/edac/altr,socfpga-ecc-manager.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Altera SoCFPGA ECC Manager

maintainers:
  - Matthew Gerlach <matthew.gerlach@altera.com>

description:
  This binding describes the device tree nodes required for the Altera SoCFPGA
  ECC Manager for the Cyclone5, Arria5, Arria10, Stratix10, and Agilex chip
  families.

properties:

  compatible:
    oneOf:
      - items:
          - const: altr,socfpga-s10-ecc-manager
          - const: altr,socfpga-a10-ecc-manager
      - const: altr,socfpga-a10-ecc-manager
      - const: altr,socfpga-ecc-manager

  "#address-cells":
    const: 1

  "#size-cells":
    const: 1

  interrupts:
    minItems: 1
    maxItems: 2

  interrupt-controller: true

  "#interrupt-cells":
    const: 2

  ranges: true

  altr,sysmgr-syscon:
    $ref: /schemas/types.yaml#/definitions/phandle
    description: phandle to Stratix10 System Manager Block with the ECC manager registers

  sdramedac:
    type: object
    additionalProperties: false

    properties:
      compatible:
        enum:
          - altr,sdram-edac-a10
          - altr,sdram-edac-s10

      interrupts:
        minItems: 1
        maxItems: 2

      altr,sdr-syscon:
        $ref: /schemas/types.yaml#/definitions/phandle
        description: phandle to SDRAM parent

    required:
      - compatible
      - interrupts
      - altr,sdr-syscon

patternProperties:
  "^ocram-ecc@[a-f0-9]+$":
    type: object
    additionalProperties: false

    properties:
      compatible:
        oneOf:
          - items:
              - const: altr,socfpga-s10-ocram-ecc
              - const: altr,socfpga-a10-ocram-ecc
          - const: altr,socfpga-a10-ocram-ecc
          - const: altr,socfpga-ocram-ecc

      reg:
        maxItems: 1

      interrupts:
        minItems: 1
        maxItems: 2

      iram:
        $ref: /schemas/types.yaml#/definitions/phandle
        description: phandle to OCRAM parent

      altr,ecc-parent:
        $ref: /schemas/types.yaml#/definitions/phandle
        description: phandle to OCRAM parent

    required:
      - compatible
      - reg
      - interrupts

  "^usb[0-9]-ecc@[a-f0-9]+$":
    type: object
    additionalProperties: false

    properties:
      compatible:
        oneOf:
          - items:
              - const: altr,socfpga-s10-usb-ecc
              - const: altr,socfpga-usb-ecc
          - const: altr,socfpga-usb-ecc

      reg:
        maxItems: 1

      interrupts:
        minItems: 1
        maxItems: 2

      altr,ecc-parent:
        $ref: /schemas/types.yaml#/definitions/phandle
        description: phandle to USB parent

    required:
      - compatible
      - reg
      - interrupts
      - altr,ecc-parent

  "^emac[0-9]-[t,r]x-ecc@[a-f0-9]+$":
    type: object
    additionalProperties: false

    properties:
      compatible:
        oneOf:
          - items:
              - const: altr,socfpga-s10-eth-mac-ecc
              - const: altr,socfpga-eth-mac-ecc
          - const: altr,socfpga-eth-mac-ecc

      reg:
        maxItems: 1

      interrupts:
        minItems: 1
        maxItems: 2

      altr,ecc-parent:
        $ref: /schemas/types.yaml#/definitions/phandle
        description: phandle to ethernet parent

    required:
      - compatible
      - reg
      - interrupts
      - altr,ecc-parent

  "^sdmmc[a-f]-ecc@[a-f0-9]+$":
    type: object
    additionalProperties: false

    properties:
      compatible:
        oneOf:
          - items:
              - const: altr,socfpga-s10-sdmmc-ecc
              - const: altr,socfpga-sdmmc-ecc
          - const: altr,socfpga-sdmmc-ecc

      reg:
        maxItems: 1

      interrupts:
        minItems: 2
        maxItems: 4

      altr,ecc-parent:
        $ref: /schemas/types.yaml#/definitions/phandle
        description: phandle to SD/MMC parent

    required:
      - compatible
      - reg
      - interrupts
      - altr,ecc-parent

  "^l2-ecc@[a-f0-9]+$":
    type: object
    additionalProperties: false

    properties:
      compatible:
        enum:
          - altr,socfpga-a10-l2-ecc
          - altr,socfpga-l2-ecc

      reg:
        maxItems: 1

      interrupts:
        maxItems: 2

    required:
      - compatible
      - reg
      - interrupts

  "^dma-ecc@[a-f0-9]+$":
    type: object
    additionalProperties: false

    properties:
      compatible:
        const: altr,socfpga-dma-ecc
      reg:
        maxItems: 1

      interrupts:
        maxItems: 2

      altr,ecc-parent:
        $ref: /schemas/types.yaml#/definitions/phandle
        description: phandle to SD/MMC parent

    required:
      - compatible
      - reg
      - interrupts
      - altr,ecc-parent

if:
  properties:
    compatible:
      contains:
        const: altr,socfpga-ecc-manager
then:
  required:
    - compatible
    - "#address-cells"
    - "#size-cells"
    - ranges

else:
  required:
    - compatible
    - "#address-cells"
    - "#size-cells"
    - interrupts
    - interrupt-controller
    - "#interrupt-cells"
    - ranges
    - altr,sysmgr-syscon

additionalProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/arm-gic.h>
    #include <dt-bindings/interrupt-controller/irq.h>
    eccmgr {
        compatible = "altr,socfpga-s10-ecc-manager",
                     "altr,socfpga-a10-ecc-manager";
        altr,sysmgr-syscon = <&sysmgr>;
        #address-cells = <1>;
        #size-cells = <1>;
        interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
        interrupt-controller;
        #interrupt-cells = <2>;
        ranges;

        sdramedac {
            compatible = "altr,sdram-edac-s10";
            altr,sdr-syscon = <&sdr>;
            interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
        };

        ocram-ecc@ff8cc000 {
            compatible = "altr,socfpga-s10-ocram-ecc",
                         "altr,socfpga-a10-ocram-ecc";
            reg = <0xff8cc000 0x100>;
            altr,ecc-parent = <&ocram>;
            interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
        };

        usb0-ecc@ff8c4000 {
            compatible = "altr,socfpga-s10-usb-ecc",
                         "altr,socfpga-usb-ecc";
            reg = <0xff8c4000 0x100>;
            altr,ecc-parent = <&usb0>;
            interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
        };

        emac0-rx-ecc@ff8c0000 {
            compatible = "altr,socfpga-s10-eth-mac-ecc",
                         "altr,socfpga-eth-mac-ecc";
            reg = <0xff8c0000 0x100>;
            altr,ecc-parent = <&gmac0>;
            interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
        };

        emac0-tx-ecc@ff8c0400 {
            compatible = "altr,socfpga-s10-eth-mac-ecc",
                         "altr,socfpga-eth-mac-ecc";
            reg = <0xff8c0400 0x100>;
            altr,ecc-parent = <&gmac0>;
            interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
        };

        sdmmca-ecc@ff8c8c00 {
            compatible = "altr,socfpga-s10-sdmmc-ecc",
                         "altr,socfpga-sdmmc-ecc";
            reg = <0xff8c8c00 0x100>;
            altr,ecc-parent = <&mmc>;
            interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
                         <15 IRQ_TYPE_LEVEL_HIGH>;
        };
    };
+0 −383
Original line number Diff line number Diff line
Altera SoCFPGA ECC Manager
This driver uses the EDAC framework to implement the SOCFPGA ECC Manager.
The ECC Manager counts and corrects single bit errors and counts/handles
double bit errors which are uncorrectable.

Cyclone5 and Arria5 ECC Manager
Required Properties:
- compatible : Should be "altr,socfpga-ecc-manager"
- #address-cells: must be 1
- #size-cells: must be 1
- ranges : standard definition, should translate from local addresses

Subcomponents:

L2 Cache ECC
Required Properties:
- compatible : Should be "altr,socfpga-l2-ecc"
- reg : Address and size for ECC error interrupt clear registers.
- interrupts : Should be single bit error interrupt, then double bit error
	interrupt. Note the rising edge type.

On Chip RAM ECC
Required Properties:
- compatible : Should be "altr,socfpga-ocram-ecc"
- reg : Address and size for ECC error interrupt clear registers.
- iram : phandle to On-Chip RAM definition.
- interrupts : Should be single bit error interrupt, then double bit error
	interrupt. Note the rising edge type.

Example:

	eccmgr: eccmgr@ffd08140 {
		compatible = "altr,socfpga-ecc-manager";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		l2-ecc@ffd08140 {
			compatible = "altr,socfpga-l2-ecc";
			reg = <0xffd08140 0x4>;
			interrupts = <0 36 1>, <0 37 1>;
		};

		ocram-ecc@ffd08144 {
			compatible = "altr,socfpga-ocram-ecc";
			reg = <0xffd08144 0x4>;
			iram = <&ocram>;
			interrupts = <0 178 1>, <0 179 1>;
		};
	};

Arria10 SoCFPGA ECC Manager
The Arria10 SoC ECC Manager handles the IRQs for each peripheral
in a shared register instead of individual IRQs like the Cyclone5
and Arria5. Therefore the device tree is different as well.

Required Properties:
- compatible : Should be "altr,socfpga-a10-ecc-manager"
- altr,sysgr-syscon : phandle to Arria10 System Manager Block
	containing the ECC manager registers.
- #address-cells: must be 1
- #size-cells: must be 1
- interrupts : Should be single bit error interrupt, then double bit error
	interrupt.
- interrupt-controller : boolean indicator that ECC Manager is an interrupt controller
- #interrupt-cells : must be set to 2.
- ranges : standard definition, should translate from local addresses

Subcomponents:

L2 Cache ECC
Required Properties:
- compatible : Should be "altr,socfpga-a10-l2-ecc"
- reg : Address and size for ECC error interrupt clear registers.
- interrupts : Should be single bit error interrupt, then double bit error
	interrupt, in this order.

On-Chip RAM ECC
Required Properties:
- compatible : Should be "altr,socfpga-a10-ocram-ecc"
- reg        : Address and size for ECC block registers.
- interrupts : Should be single bit error interrupt, then double bit error
	interrupt, in this order.

Ethernet FIFO ECC
Required Properties:
- compatible      : Should be "altr,socfpga-eth-mac-ecc"
- reg             : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent Ethernet node.
- interrupts      : Should be single bit error interrupt, then double bit error
	interrupt, in this order.

NAND FIFO ECC
Required Properties:
- compatible      : Should be "altr,socfpga-nand-ecc"
- reg             : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent NAND node.
- interrupts      : Should be single bit error interrupt, then double bit error
	interrupt, in this order.

DMA FIFO ECC
Required Properties:
- compatible      : Should be "altr,socfpga-dma-ecc"
- reg             : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent DMA node.
- interrupts      : Should be single bit error interrupt, then double bit error
	interrupt, in this order.

USB FIFO ECC
Required Properties:
- compatible      : Should be "altr,socfpga-usb-ecc"
- reg             : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent USB node.
- interrupts      : Should be single bit error interrupt, then double bit error
	interrupt, in this order.

QSPI FIFO ECC
Required Properties:
- compatible      : Should be "altr,socfpga-qspi-ecc"
- reg             : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent QSPI node.
- interrupts      : Should be single bit error interrupt, then double bit error
	interrupt, in this order.

SDMMC FIFO ECC
Required Properties:
- compatible      : Should be "altr,socfpga-sdmmc-ecc"
- reg             : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent SD/MMC node.
- interrupts      : Should be single bit error interrupt, then double bit error
	interrupt, in this order for port A, and then single bit error interrupt,
	then double bit error interrupt in this order for port B.

Example:

	eccmgr: eccmgr@ffd06000 {
		compatible = "altr,socfpga-a10-ecc-manager";
		altr,sysmgr-syscon = <&sysmgr>;
		#address-cells = <1>;
		#size-cells = <1>;
		interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>,
			     <0 0 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ranges;

		l2-ecc@ffd06010 {
			compatible = "altr,socfpga-a10-l2-ecc";
			reg = <0xffd06010 0x4>;
			interrupts = <0 IRQ_TYPE_LEVEL_HIGH>,
				     <32 IRQ_TYPE_LEVEL_HIGH>;
		};

		ocram-ecc@ff8c3000 {
			compatible = "altr,socfpga-a10-ocram-ecc";
			reg = <0xff8c3000 0x90>;
			interrupts = <1 IRQ_TYPE_LEVEL_HIGH>,
				     <33 IRQ_TYPE_LEVEL_HIGH> ;
		};

		emac0-rx-ecc@ff8c0800 {
			compatible = "altr,socfpga-eth-mac-ecc";
			reg = <0xff8c0800 0x400>;
			altr,ecc-parent = <&gmac0>;
			interrupts = <4 IRQ_TYPE_LEVEL_HIGH>,
				     <36 IRQ_TYPE_LEVEL_HIGH>;
		};

		emac0-tx-ecc@ff8c0c00 {
			compatible = "altr,socfpga-eth-mac-ecc";
			reg = <0xff8c0c00 0x400>;
			altr,ecc-parent = <&gmac0>;
			interrupts = <5 IRQ_TYPE_LEVEL_HIGH>,
				     <37 IRQ_TYPE_LEVEL_HIGH>;
		};

		nand-buf-ecc@ff8c2000 {
			compatible = "altr,socfpga-nand-ecc";
			reg = <0xff8c2000 0x400>;
			altr,ecc-parent = <&nand>;
			interrupts = <11 IRQ_TYPE_LEVEL_HIGH>,
				     <43 IRQ_TYPE_LEVEL_HIGH>;
		};

		nand-rd-ecc@ff8c2400 {
			compatible = "altr,socfpga-nand-ecc";
			reg = <0xff8c2400 0x400>;
			altr,ecc-parent = <&nand>;
			interrupts = <13 IRQ_TYPE_LEVEL_HIGH>,
				     <45 IRQ_TYPE_LEVEL_HIGH>;
		};

		nand-wr-ecc@ff8c2800 {
			compatible = "altr,socfpga-nand-ecc";
			reg = <0xff8c2800 0x400>;
			altr,ecc-parent = <&nand>;
			interrupts = <12 IRQ_TYPE_LEVEL_HIGH>,
				     <44 IRQ_TYPE_LEVEL_HIGH>;
		};

		dma-ecc@ff8c8000 {
			compatible = "altr,socfpga-dma-ecc";
			reg = <0xff8c8000 0x400>;
			altr,ecc-parent = <&pdma>;
			interrupts = <10 IRQ_TYPE_LEVEL_HIGH>,
				     <42 IRQ_TYPE_LEVEL_HIGH>;

		usb0-ecc@ff8c8800 {
			compatible = "altr,socfpga-usb-ecc";
			reg = <0xff8c8800 0x400>;
			altr,ecc-parent = <&usb0>;
			interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
				     <34 IRQ_TYPE_LEVEL_HIGH>;
		};

		qspi-ecc@ff8c8400 {
			compatible = "altr,socfpga-qspi-ecc";
			reg = <0xff8c8400 0x400>;
			altr,ecc-parent = <&qspi>;
			interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
				     <46 IRQ_TYPE_LEVEL_HIGH>;
		};

		sdmmc-ecc@ff8c2c00 {
			compatible = "altr,socfpga-sdmmc-ecc";
			reg = <0xff8c2c00 0x400>;
			altr,ecc-parent = <&mmc>;
			interrupts = <15 IRQ_TYPE_LEVEL_HIGH>,
				     <47 IRQ_TYPE_LEVEL_HIGH>,
				     <16 IRQ_TYPE_LEVEL_HIGH>,
				     <48 IRQ_TYPE_LEVEL_HIGH>;
		};
	};

Stratix10 SoCFPGA ECC Manager (ARM64)
The Stratix10 SoC ECC Manager handles the IRQs for each peripheral
in a shared register similar to the Arria10. However, Stratix10 ECC
requires access to registers that can only be read from Secure Monitor
with SMC calls. Therefore the device tree is slightly different. Note
that only 1 interrupt is sent in Stratix10 because the double bit errors
are treated as SErrors in ARM64 instead of IRQs in ARM32.

Required Properties:
- compatible : Should be "altr,socfpga-s10-ecc-manager"
- altr,sysgr-syscon : phandle to Stratix10 System Manager Block
	              containing the ECC manager registers.
- interrupts : Should be single bit error interrupt.
- interrupt-controller : boolean indicator that ECC Manager is an interrupt controller
- #interrupt-cells : must be set to 2.
- #address-cells: must be 1
- #size-cells: must be 1
- ranges : standard definition, should translate from local addresses

Subcomponents:

SDRAM ECC
Required Properties:
- compatible : Should be "altr,sdram-edac-s10"
- interrupts : Should be single bit error interrupt.

On-Chip RAM ECC
Required Properties:
- compatible      : Should be "altr,socfpga-s10-ocram-ecc"
- reg             : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent OCRAM node.
- interrupts      : Should be single bit error interrupt.

Ethernet FIFO ECC
Required Properties:
- compatible      : Should be "altr,socfpga-s10-eth-mac-ecc"
- reg             : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent Ethernet node.
- interrupts      : Should be single bit error interrupt.

NAND FIFO ECC
Required Properties:
- compatible      : Should be "altr,socfpga-s10-nand-ecc"
- reg             : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent NAND node.
- interrupts      : Should be single bit error interrupt.

DMA FIFO ECC
Required Properties:
- compatible      : Should be "altr,socfpga-s10-dma-ecc"
- reg             : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent DMA node.
- interrupts      : Should be single bit error interrupt.

USB FIFO ECC
Required Properties:
- compatible      : Should be "altr,socfpga-s10-usb-ecc"
- reg             : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent USB node.
- interrupts      : Should be single bit error interrupt.

SDMMC FIFO ECC
Required Properties:
- compatible      : Should be "altr,socfpga-s10-sdmmc-ecc"
- reg             : Address and size for ECC block registers.
- altr,ecc-parent : phandle to parent SD/MMC node.
- interrupts      : Should be single bit error interrupt for port A
		    and then single bit error interrupt for port B.

Example:

	eccmgr {
		compatible = "altr,socfpga-s10-ecc-manager";
		altr,sysmgr-syscon = <&sysmgr>;
		#address-cells = <1>;
		#size-cells = <1>;
		interrupts = <0 15 4>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ranges;

		sdramedac {
			compatible = "altr,sdram-edac-s10";
			interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
		};

		ocram-ecc@ff8cc000 {
			compatible = "altr,socfpga-s10-ocram-ecc";
			reg = <ff8cc000 0x100>;
			altr,ecc-parent = <&ocram>;
			interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
		};

		emac0-rx-ecc@ff8c0000 {
			compatible = "altr,socfpga-s10-eth-mac-ecc";
			reg = <0xff8c0000 0x100>;
			altr,ecc-parent = <&gmac0>;
			interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
		};

		emac0-tx-ecc@ff8c0400 {
			compatible = "altr,socfpga-s10-eth-mac-ecc";
			reg = <0xff8c0400 0x100>;
			altr,ecc-parent = <&gmac0>;
			interrupts = <5 IRQ_TYPE_LEVEL_HIGH>'
		};

		nand-buf-ecc@ff8c8000 {
			compatible = "altr,socfpga-s10-nand-ecc";
			reg = <0xff8c8000 0x100>;
			altr,ecc-parent = <&nand>;
			interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
		};

		nand-rd-ecc@ff8c8400 {
			compatible = "altr,socfpga-s10-nand-ecc";
			reg = <0xff8c8400 0x100>;
			altr,ecc-parent = <&nand>;
			interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
		};

		nand-wr-ecc@ff8c8800 {
			compatible = "altr,socfpga-s10-nand-ecc";
			reg = <0xff8c8800 0x100>;
			altr,ecc-parent = <&nand>;
			interrupts = <12 IRQ_TYPE_LEVEL_HIGH>;
		};

		dma-ecc@ff8c9000 {
			compatible = "altr,socfpga-s10-dma-ecc";
			reg = <0xff8c9000 0x100>;
			altr,ecc-parent = <&pdma>;
			interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;

		usb0-ecc@ff8c4000 {
			compatible = "altr,socfpga-s10-usb-ecc";
			reg = <0xff8c4000 0x100>;
			altr,ecc-parent = <&usb0>;
			interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
		};

		sdmmc-ecc@ff8c8c00 {
			compatible = "altr,socfpga-s10-sdmmc-ecc";
			reg = <0xff8c8c00 0x100>;
			altr,ecc-parent = <&mmc>;
			interrupts = <14 IRQ_TYPE_LEVEL_HIGH>,
				     <15 IRQ_TYPE_LEVEL_HIGH>;
		};
	};
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