Commit 3bd0edf8 authored by Jacek Lawrynowicz's avatar Jacek Lawrynowicz
Browse files

accel/ivpu: Update FW API headers 



Update Boot API to 3.22.0 and JSM API to 3.15.6

Signed-off-by: default avatarJacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com>
Reviewed-by: default avatarJeffrey Hugo <quic_jhugo@quicinc.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240214081305.290108-4-jacek.lawrynowicz@linux.intel.com
parent 575fcdd3

drivers/accel/ivpu/vpu_boot_api.h

+33 −13
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: MIT */

/*

 * Copyright (C) 2020-2023 Intel Corporation

 * Copyright (c) 2020-2023, Intel Corporation.

 */



#ifndef VPU_BOOT_API_H
@@ -27,12 +27,12 @@ 
 * Minor version changes when API backward compatibility is preserved.

 * Resets to 0 if Major version is incremented.

 */

#define VPU_BOOT_API_VER_MINOR 20

#define VPU_BOOT_API_VER_MINOR 22



/*

 * API header changed (field names, documentation, formatting) but API itself has not been changed

 */

#define VPU_BOOT_API_VER_PATCH 4

#define VPU_BOOT_API_VER_PATCH 0



/*

 * Index in the API version table
@@ -41,7 +41,7 @@ 
#define VPU_BOOT_API_VER_INDEX 0

/* ------------ FW API version information end ---------------------*/



#pragma pack(push, 1)

#pragma pack(push, 4)



/*

 * Firmware image header format
@@ -66,9 +66,17 @@ struct vpu_firmware_header { 
	/* Size of memory require for firmware execution */

	u32 runtime_size;

	u32 shave_nn_fw_size;

	/* Size of primary preemption buffer. */

	/*

	 * Size of primary preemption buffer, assuming a 2-job submission queue.

	 * NOTE: host driver is expected to adapt size accordingly to actual

	 * submission queue size and device capabilities.

	 */

	u32 preemption_buffer_1_size;

	/* Size of secondary preemption buffer. */

	/*

	 * Size of secondary preemption buffer, assuming a 2-job submission queue.

	 * NOTE: host driver is expected to adapt size accordingly to actual

	 * submission queue size and device capabilities.

	 */

	u32 preemption_buffer_2_size;

	/* Space reserved for future preemption-related fields. */

	u32 preemption_reserved[6];
@@ -181,10 +189,10 @@ struct vpu_warm_boot_section { 
#define VPU_PRESENT_CALL_PERIOD_MS_MAX	   10000



/**

 * Macros to enable various operation modes within the VPU.

 * Macros to enable various power profiles within the NPU.

 * To be defined as part of 32 bit mask.

 */

#define VPU_OP_MODE_SURVIVABILITY 0x1

#define POWER_PROFILE_SURVIVABILITY 0x1



struct vpu_boot_params {

	u32 magic;
@@ -317,7 +325,15 @@ struct vpu_boot_params { 
	u64 d0i3_residency_time_us;

	/* Value of VPU perf counter at the time of entering D0i3 state . */

	u64 d0i3_entry_vpu_ts;

	u32 pad4[20];

	/*

	 * The system time of the host operating system in microseconds.

	 * E.g the number of microseconds since 1st of January 1970, or whatever date the

	 * host operating system uses to maintain system time.

	 * This value will be used to track system time on the VPU.

	 * The KMD is required to update this value on every VPU reset.

	 */

	u64 system_time_us;

	u32 pad4[18];

	/* Warm boot information: 0x400 - 0x43F */

	u32 warm_boot_sections_count;

	u32 warm_boot_start_address_reference;
@@ -344,10 +360,14 @@ struct vpu_boot_params { 
	u32 vpu_focus_present_timer_ms;

	/* VPU ECC Signaling */

	u32 vpu_uses_ecc_mca_signal;

	/* Values defined by VPU_OP_MODE* macros */

	u32 vpu_operation_mode;

	/* Unused/reserved: 0x480 - 0xFFF */

	u32 pad6[736];

	/* Values defined by POWER_PROFILE* macros */

	u32 power_profile;

	/* Microsecond value for DCT active cycle */

	u32 dct_active_us;

	/* Microsecond value for DCT inactive cycle */

	u32 dct_inactive_us;

	/* Unused/reserved: 0x488 - 0xFFF */

	u32 pad6[734];

};



/*

drivers/accel/ivpu/vpu_jsm_api.h

+22 −10
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: MIT */

/*

 * Copyright (C) 2020-2023 Intel Corporation

 * Copyright (c) 2020-2023, Intel Corporation.

 */



/**
@@ -27,7 +27,7 @@ 
/*

 * API header changed (field names, documentation, formatting) but API itself has not been changed

 */

#define VPU_JSM_API_VER_PATCH 0

#define VPU_JSM_API_VER_PATCH 6



/*

 * Index in the API version table
@@ -43,8 +43,11 @@ 
/* Max number of impacted contexts that can be dealt with the engine reset command */

#define VPU_MAX_ENGINE_RESET_IMPACTED_CONTEXTS 3



/** Pack the API structures for now, once alignment issues are fixed this can be removed */

#pragma pack(push, 1)

/*

 * Pack the API structures to enforce binary compatibility

 * Align to 8 bytes for optimal performance

 */

#pragma pack(push, 8)



/*

 * Engine indexes.
@@ -124,6 +127,19 @@ 
 */

#define VPU_HWS_MAX_REALTIME_PRIORITY_LEVEL 31U



/*

 * vpu_jsm_engine_reset_context flag definitions

 */

#define VPU_ENGINE_RESET_CONTEXT_FLAG_COLLATERAL_DAMAGE_MASK BIT(0)

#define VPU_ENGINE_RESET_CONTEXT_HANG_PRIMARY_CAUSE	     0

#define VPU_ENGINE_RESET_CONTEXT_COLLATERAL_DAMAGE	     1



/*

 * Invalid command queue handle identifier. Applies to cmdq_id and cmdq_group

 * in this API.

 */

#define VPU_HWS_INVALID_CMDQ_HANDLE 0ULL



/*

 * Job format.

 */
@@ -613,7 +629,7 @@ struct vpu_jsm_engine_reset_context { 
	u32 reserved_0;

	/* Command queue id */

	u64 cmdq_id;

	/* Flags: 0: cause of hang; 1: collateral damage of reset */

	/* See VPU_ENGINE_RESET_CONTEXT_* defines */

	u64 flags;

};
@@ -730,11 +746,7 @@ struct vpu_ipc_msg_payload_hws_create_cmdq { 
	u32 host_ssid;

	/* Engine for which queue is being created */

	u32 engine_idx;

	/*

	 * Cmdq group may be set to 0 or equal to

	 * cmdq_id while each priority band contains

	 * only single engine instances.

	 */

	/* Cmdq group: only used for HWS logging of state changes */

	u64 cmdq_group;

	/* Command queue id */

	u64 cmdq_id;