Commit 3efadf02 authored by Junxiao Chang's avatar Junxiao Chang Committed by Maarten Lankhorst
Browse files

drm/me/gsc: mei interrupt top half should be in irq disabled context 



MEI GSC interrupt comes from i915 or xe driver. It has top half and
bottom half. Top half is called from i915/xe interrupt handler. It
should be in irq disabled context.

With RT kernel(PREEMPT_RT enabled), by default IRQ handler is in
threaded IRQ. MEI GSC top half might be in threaded IRQ context.
generic_handle_irq_safe API could be called from either IRQ or
process context, it disables local IRQ then calls MEI GSC interrupt
top half.

This change fixes B580 GPU boot issue with RT enabled.

Fixes: e02cea83 ("drm/xe/gsc: add Battlemage support")
Tested-by: default avatarBaoli Zhang <baoli.zhang@intel.com>
Signed-off-by: default avatarJunxiao Chang <junxiao.chang@intel.com>
Reviewed-by: default avatarSebastian Andrzej Siewior <bigeasy@linutronix.de>
Reviewed-by: default avatarMatthew Brost <matthew.brost@intel.com>
Link: https://patch.msgid.link/20251107033152.834960-1-junxiao.chang@intel.com


Signed-off-by: default avatarMaarten Lankhorst <dev@lankhorst.se>
parent 1898840d

drivers/gpu/drm/xe/xe_heci_gsc.c

+2 −2
Original line number Diff line number Diff line
@@ -223,7 +223,7 @@ void xe_heci_gsc_irq_handler(struct xe_device *xe, u32 iir) 
	if (xe->heci_gsc.irq < 0)

		return;



	ret = generic_handle_irq(xe->heci_gsc.irq);

	ret = generic_handle_irq_safe(xe->heci_gsc.irq);

	if (ret)

		drm_err_ratelimited(&xe->drm, "error handling GSC irq: %d\n", ret);

}
@@ -243,7 +243,7 @@ void xe_heci_csc_irq_handler(struct xe_device *xe, u32 iir) 
	if (xe->heci_gsc.irq < 0)

		return;



	ret = generic_handle_irq(xe->heci_gsc.irq);

	ret = generic_handle_irq_safe(xe->heci_gsc.irq);

	if (ret)

		drm_err_ratelimited(&xe->drm, "error handling GSC irq: %d\n", ret);

}