Commit 3f3f64cb authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux 

Pull arm64 fixes from Will Deacon:
 "It's a little busier than normal, but it's still not a lot of code and
  things seem fairly quiet in general:

   - Fix allocation failure during SVE coredumps

   - Fix handling of SVE context on signal delivery

   - Enable Neoverse N2 CPU errata workarounds for Microsoft's "Azure
     Cobalt 100" clone

   - Work around CMN PMU erratum in AmpereOneX implementation

   - Fix typo in CXL PMU event definition

   - Fix jump label asm constraints"

* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
  arm64/sve: Lower the maximum allocation for the SVE ptrace regset
  arm64: Subscribe Microsoft Azure Cobalt 100 to ARM Neoverse N2 errata
  perf/arm-cmn: Workaround AmpereOneX errata AC04_MESH_1 (incorrect child count)
  arm64: jump_label: use constraints "Si" instead of "i"
  arm64: fix typo in comments
  perf: CXL: fix mismatched cpmu event opcode
  arm64/signal: Don't assume that TIF_SVE means we saved SVE state
parents efb0b63a 28139262

Documentation/arch/arm64/silicon-errata.rst

+7 −0
Original line number Diff line number Diff line
@@ -243,3 +243,10 @@ stable kernels. 
+----------------+-----------------+-----------------+-----------------------------+

| ASR            | ASR8601         | #8601001        | N/A                         |

+----------------+-----------------+-----------------+-----------------------------+

+----------------+-----------------+-----------------+-----------------------------+

| Microsoft      | Azure Cobalt 100| #2139208        | ARM64_ERRATUM_2139208       |

+----------------+-----------------+-----------------+-----------------------------+

| Microsoft      | Azure Cobalt 100| #2067961        | ARM64_ERRATUM_2067961       |

+----------------+-----------------+-----------------+-----------------------------+

| Microsoft      | Azure Cobalt 100| #2253138        | ARM64_ERRATUM_2253138       |

+----------------+-----------------+-----------------+-----------------------------+

arch/arm64/include/asm/cpufeature.h

+1 −1
Original line number Diff line number Diff line
@@ -83,7 +83,7 @@ struct arm64_ftr_bits { 
 * to full-0 denotes that this field has no override

 *

 * A @mask field set to full-0 with the corresponding @val field set

 * to full-1 denotes thath this field has an invalid override.

 * to full-1 denotes that this field has an invalid override.

 */

struct arm64_ftr_override {

	u64		val;

arch/arm64/include/asm/cputype.h

+4 −0
Original line number Diff line number Diff line
@@ -61,6 +61,7 @@ 
#define ARM_CPU_IMP_HISI		0x48

#define ARM_CPU_IMP_APPLE		0x61

#define ARM_CPU_IMP_AMPERE		0xC0

#define ARM_CPU_IMP_MICROSOFT		0x6D



#define ARM_CPU_PART_AEM_V8		0xD0F

#define ARM_CPU_PART_FOUNDATION		0xD00
@@ -135,6 +136,8 @@ 


#define AMPERE_CPU_PART_AMPERE1		0xAC3



#define MICROSOFT_CPU_PART_AZURE_COBALT_100	0xD49 /* Based on r0p0 of ARM Neoverse N2 */



#define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)

#define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)

#define MIDR_CORTEX_A72 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A72)
@@ -193,6 +196,7 @@ 
#define MIDR_APPLE_M2_BLIZZARD_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_BLIZZARD_MAX)

#define MIDR_APPLE_M2_AVALANCHE_MAX MIDR_CPU_MODEL(ARM_CPU_IMP_APPLE, APPLE_CPU_PART_M2_AVALANCHE_MAX)

#define MIDR_AMPERE1 MIDR_CPU_MODEL(ARM_CPU_IMP_AMPERE, AMPERE_CPU_PART_AMPERE1)

#define MIDR_MICROSOFT_AZURE_COBALT_100 MIDR_CPU_MODEL(ARM_CPU_IMP_MICROSOFT, MICROSOFT_CPU_PART_AZURE_COBALT_100)



/* Fujitsu Erratum 010001 affects A64FX 1.0 and 1.1, (v0r0 and v1r0) */

#define MIDR_FUJITSU_ERRATUM_010001		MIDR_FUJITSU_A64FX

arch/arm64/include/asm/fpsimd.h

+6 −6
Original line number Diff line number Diff line
@@ -62,13 +62,13 @@ static inline void cpacr_restore(unsigned long cpacr) 
 * When we defined the maximum SVE vector length we defined the ABI so

 * that the maximum vector length included all the reserved for future

 * expansion bits in ZCR rather than those just currently defined by

 * the architecture. While SME follows a similar pattern the fact that

 * it includes a square matrix means that any allocations that attempt

 * to cover the maximum potential vector length (such as happen with

 * the regset used for ptrace) end up being extremely large. Define

 * the much lower actual limit for use in such situations.

 * the architecture.  Using this length to allocate worst size buffers

 * results in excessively large allocations, and this effect is even

 * more pronounced for SME due to ZA.  Define more suitable VLs for

 * these situations.

 */

#define SME_VQ_MAX	16

#define ARCH_SVE_VQ_MAX ((ZCR_ELx_LEN_MASK >> ZCR_ELx_LEN_SHIFT) + 1)

#define SME_VQ_MAX	((SMCR_ELx_LEN_MASK >> SMCR_ELx_LEN_SHIFT) + 1)



struct task_struct;

arch/arm64/include/asm/jump_label.h

+8 −4
Original line number Diff line number Diff line
@@ -15,6 +15,10 @@ 


#define JUMP_LABEL_NOP_SIZE		AARCH64_INSN_SIZE



/*

 * Prefer the constraint "S" to support PIC with GCC. Clang before 19 does not

 * support "S" on a symbol with a constant offset, so we use "i" as a fallback.

 */

static __always_inline bool arch_static_branch(struct static_key * const key,

					       const bool branch)

{
@@ -23,9 +27,9 @@ static __always_inline bool arch_static_branch(struct static_key * const key, 
		 "	.pushsection	__jump_table, \"aw\"	\n\t"

		 "	.align		3			\n\t"

		 "	.long		1b - ., %l[l_yes] - .	\n\t"

		 "	.quad		%c0 - .			\n\t"

		 "	.quad		(%[key] - .) + %[bit0]  \n\t"

		 "	.popsection				\n\t"

		 :  :  "i"(&((char *)key)[branch]) :  : l_yes);

		 :  :  [key]"Si"(key), [bit0]"i"(branch) :  : l_yes);



	return false;

l_yes:
@@ -40,9 +44,9 @@ static __always_inline bool arch_static_branch_jump(struct static_key * const ke 
		 "	.pushsection	__jump_table, \"aw\"	\n\t"

		 "	.align		3			\n\t"

		 "	.long		1b - ., %l[l_yes] - .	\n\t"

		 "	.quad		%c0 - .			\n\t"

		 "	.quad		(%[key] - .) + %[bit0]  \n\t"

		 "	.popsection				\n\t"

		 :  :  "i"(&((char *)key)[branch]) :  : l_yes);

		 :  :  [key]"Si"(key), [bit0]"i"(branch) :  : l_yes);



	return false;

l_yes: