Commit 3f67782e authored by Jakub Kicinski's avatar Jakub Kicinski
Browse files

Merge branch 'bnxt_en-bug-fixes-for-net' 

Michael Chan says:

====================
bnxt_en: Bug fixes for net

The first firmware interface update is needed by the second patch to
limit the number of TSO segments on the 5760X chips.  The third patch
fixes the TX error path for PTP packets.
====================

Link: https://lore.kernel.org/r/20240618215313.29631-1-michael.chan@broadcom.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parents 88513469 1e796211

drivers/net/ethernet/broadcom/bnxt/bnxt.c

+5 −3
Original line number Diff line number Diff line
@@ -732,9 +732,6 @@ static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev) 
	return NETDEV_TX_OK;



tx_dma_error:

	if (BNXT_TX_PTP_IS_SET(lflags))

		atomic_inc(&bp->ptp_cfg->tx_avail);



	last_frag = i;



	/* start back at beginning and unmap skb */
@@ -756,6 +753,8 @@ static netdev_tx_t bnxt_start_xmit(struct sk_buff *skb, struct net_device *dev) 
tx_free:

	dev_kfree_skb_any(skb);

tx_kick_pending:

	if (BNXT_TX_PTP_IS_SET(lflags))

		atomic_inc(&bp->ptp_cfg->tx_avail);

	if (txr->kick_pending)

		bnxt_txr_db_kick(bp, txr, txr->tx_prod);

	txr->tx_buf_ring[txr->tx_prod].skb = NULL;
@@ -8996,6 +8995,7 @@ static int __bnxt_hwrm_func_qcaps(struct bnxt *bp) 
		memcpy(vf->mac_addr, resp->mac_address, ETH_ALEN);

#endif

	}

	bp->tso_max_segs = le16_to_cpu(resp->max_tso_segs);



hwrm_func_qcaps_exit:

	hwrm_req_drop(bp, req);
@@ -15363,6 +15363,8 @@ static int bnxt_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 
	dev->priv_flags |= IFF_UNICAST_FLT;



	netif_set_tso_max_size(dev, GSO_MAX_SIZE);

	if (bp->tso_max_segs)

		netif_set_tso_max_segs(dev, bp->tso_max_segs);



	dev->xdp_features = NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT |

			    NETDEV_XDP_ACT_RX_SG;

drivers/net/ethernet/broadcom/bnxt/bnxt.h

+1 −0
Original line number Diff line number Diff line
@@ -2318,6 +2318,7 @@ struct bnxt { 
	u8			rss_hash_key_updated:1;



	u16			max_mtu;

	u16			tso_max_segs;

	u8			max_tc;

	u8			max_lltc;	/* lossless TCs */

	struct bnxt_queue_info	q_info[BNXT_MAX_QUEUE];

drivers/net/ethernet/broadcom/bnxt/bnxt_hsi.h

+178 −133
Original line number Diff line number Diff line
@@ -2,7 +2,7 @@ 
 *

 * Copyright (c) 2014-2016 Broadcom Corporation

 * Copyright (c) 2014-2018 Broadcom Limited

 * Copyright (c) 2018-2023 Broadcom Inc.

 * Copyright (c) 2018-2024 Broadcom Inc.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by
@@ -500,7 +500,11 @@ struct cmd_nums { 
	#define HWRM_TFC_IF_TBL_GET                       0x399UL

	#define HWRM_TFC_TBL_SCOPE_CONFIG_GET             0x39aUL

	#define HWRM_TFC_RESC_USAGE_QUERY                 0x39bUL

	#define HWRM_QUEUE_PFCWD_TIMEOUT_QCAPS            0x39cUL

	#define HWRM_QUEUE_PFCWD_TIMEOUT_CFG              0x39dUL

	#define HWRM_QUEUE_PFCWD_TIMEOUT_QCFG             0x39eUL

	#define HWRM_SV                                   0x400UL

	#define HWRM_DBG_LOG_BUFFER_FLUSH                 0xff0fUL

	#define HWRM_DBG_READ_DIRECT                      0xff10UL

	#define HWRM_DBG_READ_INDIRECT                    0xff11UL

	#define HWRM_DBG_WRITE_DIRECT                     0xff12UL
@@ -609,8 +613,8 @@ struct hwrm_err_output { 
#define HWRM_VERSION_MAJOR 1

#define HWRM_VERSION_MINOR 10

#define HWRM_VERSION_UPDATE 3

#define HWRM_VERSION_RSVD 39

#define HWRM_VERSION_STR "1.10.3.39"

#define HWRM_VERSION_RSVD 44

#define HWRM_VERSION_STR "1.10.3.44"



/* hwrm_ver_get_input (size:192b/24B) */

struct hwrm_ver_get_input {
@@ -664,6 +668,7 @@ struct hwrm_ver_get_output { 
	#define VER_GET_RESP_DEV_CAPS_CFG_CFA_TFLIB_SUPPORTED                      0x2000UL

	#define VER_GET_RESP_DEV_CAPS_CFG_CFA_TRUFLOW_SUPPORTED                    0x4000UL

	#define VER_GET_RESP_DEV_CAPS_CFG_SECURE_BOOT_CAPABLE                      0x8000UL

	#define VER_GET_RESP_DEV_CAPS_CFG_SECURE_SOC_CAPABLE                       0x10000UL

	u8	roce_fw_maj_8b;

	u8	roce_fw_min_8b;

	u8	roce_fw_bld_8b;
@@ -843,7 +848,9 @@ struct hwrm_async_event_cmpl { 
	#define ASYNC_EVENT_CMPL_EVENT_ID_HW_DOORBELL_RECOVERY_READ_ERROR 0x49UL

	#define ASYNC_EVENT_CMPL_EVENT_ID_CTX_ERROR                       0x4aUL

	#define ASYNC_EVENT_CMPL_EVENT_ID_UDCC_SESSION_CHANGE             0x4bUL

	#define ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID               0x4cUL

	#define ASYNC_EVENT_CMPL_EVENT_ID_DBG_BUF_PRODUCER                0x4cUL

	#define ASYNC_EVENT_CMPL_EVENT_ID_PEER_MMAP_CHANGE                0x4dUL

	#define ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID               0x4eUL

	#define ASYNC_EVENT_CMPL_EVENT_ID_FW_TRACE_MSG                    0xfeUL

	#define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR                      0xffUL

	#define ASYNC_EVENT_CMPL_EVENT_ID_LAST                           ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR
@@ -1814,6 +1821,9 @@ struct hwrm_func_qcaps_output { 
	#define FUNC_QCAPS_RESP_FLAGS_EXT2_SW_MAX_RESOURCE_LIMITS_SUPPORTED      0x800000UL

	#define FUNC_QCAPS_RESP_FLAGS_EXT2_TF_INGRESS_NIC_FLOW_SUPPORTED         0x1000000UL

	#define FUNC_QCAPS_RESP_FLAGS_EXT2_LPBK_STATS_SUPPORTED                  0x2000000UL

	#define FUNC_QCAPS_RESP_FLAGS_EXT2_TF_EGRESS_NIC_FLOW_SUPPORTED          0x4000000UL

	#define FUNC_QCAPS_RESP_FLAGS_EXT2_MULTI_LOSSLESS_QUEUES_SUPPORTED       0x8000000UL

	#define FUNC_QCAPS_RESP_FLAGS_EXT2_PEER_MMAP_SUPPORTED                   0x10000000UL

	__le16	tunnel_disable_flag;

	#define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_VXLAN      0x1UL

	#define FUNC_QCAPS_RESP_TUNNEL_DISABLE_FLAG_DISABLE_NGE        0x2UL
@@ -1828,7 +1838,7 @@ struct hwrm_func_qcaps_output { 
	#define FUNC_QCAPS_RESP_XID_PARTITION_CAP_RX_CK     0x2UL

	u8	device_serial_number[8];

	__le16	ctxs_per_partition;

	u8	unused_2[2];

	__le16	max_tso_segs;

	__le32	roce_vf_max_av;

	__le32	roce_vf_max_cq;

	__le32	roce_vf_max_mrw;
@@ -2449,6 +2459,7 @@ struct hwrm_func_drv_rgtr_input { 
	#define FUNC_DRV_RGTR_REQ_FLAGS_NPAR_1_2_SUPPORT                 0x200UL

	#define FUNC_DRV_RGTR_REQ_FLAGS_ASYM_QUEUE_CFG_SUPPORT           0x400UL

	#define FUNC_DRV_RGTR_REQ_FLAGS_TF_INGRESS_NIC_FLOW_MODE         0x800UL

	#define FUNC_DRV_RGTR_REQ_FLAGS_TF_EGRESS_NIC_FLOW_MODE          0x1000UL

	__le32	enables;

	#define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE             0x1UL

	#define FUNC_DRV_RGTR_REQ_ENABLES_VER                 0x2UL
@@ -3669,6 +3680,8 @@ struct hwrm_func_backing_store_cfg_v2_input { 
	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_FP_TQM_RING     0x6UL

	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_MRAV            0xeUL

	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_TIM             0xfUL

	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_TX_CK           0x13UL

	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_RX_CK           0x14UL

	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_MP_TQM_RING     0x15UL

	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_SQ_DB_SHADOW    0x16UL

	#define FUNC_BACKING_STORE_CFG_V2_REQ_TYPE_RQ_DB_SHADOW    0x17UL
@@ -3781,6 +3794,8 @@ struct hwrm_func_backing_store_qcfg_v2_output { 
	#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_FP_TQM_RING     0x6UL

	#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_MRAV            0xeUL

	#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_TIM             0xfUL

	#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_TX_CK           0x13UL

	#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_RX_CK           0x14UL

	#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_MP_TQM_RING     0x15UL

	#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_TBL_SCOPE       0x1cUL

	#define FUNC_BACKING_STORE_QCFG_V2_RESP_TYPE_XID_PARTITION   0x1dUL
@@ -3885,6 +3900,8 @@ struct hwrm_func_backing_store_qcaps_v2_input { 
	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_FP_TQM_RING     0x6UL

	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MRAV            0xeUL

	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TIM             0xfUL

	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_TX_CK           0x13UL

	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RX_CK           0x14UL

	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_MP_TQM_RING     0x15UL

	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_SQ_DB_SHADOW    0x16UL

	#define FUNC_BACKING_STORE_QCAPS_V2_REQ_TYPE_RQ_DB_SHADOW    0x17UL
@@ -3920,6 +3937,8 @@ struct hwrm_func_backing_store_qcaps_v2_output { 
	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_FP_TQM_RING     0x6UL

	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_MRAV            0xeUL

	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_TIM             0xfUL

	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_TX_CK           0x13UL

	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_RX_CK           0x14UL

	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_MP_TQM_RING     0x15UL

	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_SQ_DB_SHADOW    0x16UL

	#define FUNC_BACKING_STORE_QCAPS_V2_RESP_TYPE_RQ_DB_SHADOW    0x17UL
@@ -4202,7 +4221,8 @@ struct hwrm_port_phy_cfg_input { 
	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_100GB_PAM4_112 0x3eaUL

	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_200GB_PAM4_112 0x7d2UL

	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_112 0xfa2UL

	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_LAST          PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_400GB_PAM4_112

	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_800GB_PAM4_112 0x1f42UL

	#define PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_LAST          PORT_PHY_CFG_REQ_FORCE_LINK_SPEEDS2_800GB_PAM4_112

	__le16	auto_link_speeds2_mask;

	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_1GB                0x1UL

	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_10GB               0x2UL
@@ -4217,6 +4237,7 @@ struct hwrm_port_phy_cfg_input { 
	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_100GB_PAM4_112     0x400UL

	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_200GB_PAM4_112     0x800UL

	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_400GB_PAM4_112     0x1000UL

	#define PORT_PHY_CFG_REQ_AUTO_LINK_SPEEDS2_MASK_800GB_PAM4_112     0x2000UL

	u8	unused_2[6];

};
@@ -4292,6 +4313,7 @@ struct hwrm_port_phy_qcfg_output { 
	#define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB 0x3e8UL

	#define PORT_PHY_QCFG_RESP_LINK_SPEED_200GB 0x7d0UL

	#define PORT_PHY_QCFG_RESP_LINK_SPEED_400GB 0xfa0UL

	#define PORT_PHY_QCFG_RESP_LINK_SPEED_800GB 0x1f40UL

	#define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB  0xffffUL

	#define PORT_PHY_QCFG_RESP_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_LINK_SPEED_10MB

	u8	duplex_cfg;
@@ -4451,7 +4473,13 @@ struct hwrm_port_phy_qcfg_output { 
	#define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASESR4     0x35UL

	#define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASELR4     0x36UL

	#define PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEER4     0x37UL

	#define PORT_PHY_QCFG_RESP_PHY_TYPE_LAST            PORT_PHY_QCFG_RESP_PHY_TYPE_400G_BASEER4

	#define PORT_PHY_QCFG_RESP_PHY_TYPE_800G_BASECR8     0x38UL

	#define PORT_PHY_QCFG_RESP_PHY_TYPE_800G_BASESR8     0x39UL

	#define PORT_PHY_QCFG_RESP_PHY_TYPE_800G_BASELR8     0x3aUL

	#define PORT_PHY_QCFG_RESP_PHY_TYPE_800G_BASEER8     0x3bUL

	#define PORT_PHY_QCFG_RESP_PHY_TYPE_800G_BASEFR8     0x3cUL

	#define PORT_PHY_QCFG_RESP_PHY_TYPE_800G_BASEDR8     0x3dUL

	#define PORT_PHY_QCFG_RESP_PHY_TYPE_LAST            PORT_PHY_QCFG_RESP_PHY_TYPE_800G_BASEDR8

	u8	media_type;

	#define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN 0x0UL

	#define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP      0x1UL
@@ -5049,33 +5077,43 @@ struct hwrm_port_qstats_ext_output { 
	u8	valid;

};



/* hwrm_port_lpbk_qstats_input (size:128b/16B) */

/* hwrm_port_lpbk_qstats_input (size:256b/32B) */

struct hwrm_port_lpbk_qstats_input {

	__le16	req_type;

	__le16	cmpl_ring;

	__le16	seq_id;

	__le16	target_id;

	__le64	resp_addr;

	__le16	lpbk_stat_size;

	u8	flags;

	#define PORT_LPBK_QSTATS_REQ_FLAGS_COUNTER_MASK     0x1UL

	u8	unused_0[5];

	__le64	lpbk_stat_host_addr;

};



/* hwrm_port_lpbk_qstats_output (size:768b/96B) */

/* hwrm_port_lpbk_qstats_output (size:128b/16B) */

struct hwrm_port_lpbk_qstats_output {

	__le16	error_code;

	__le16	req_type;

	__le16	seq_id;

	__le16	resp_len;

	__le16	lpbk_stat_size;

	u8	unused_0[5];

	u8	valid;

};



/* port_lpbk_stats (size:640b/80B) */

struct port_lpbk_stats {

	__le64	lpbk_ucast_frames;

	__le64	lpbk_mcast_frames;

	__le64	lpbk_bcast_frames;

	__le64	lpbk_ucast_bytes;

	__le64	lpbk_mcast_bytes;

	__le64	lpbk_bcast_bytes;

	__le64	tx_stat_discard;

	__le64	tx_stat_error;

	__le64	rx_stat_discard;

	__le64	rx_stat_error;

	u8	unused_0[7];

	u8	valid;

	__le64	lpbk_tx_discards;

	__le64	lpbk_tx_errors;

	__le64	lpbk_rx_discards;

	__le64	lpbk_rx_errors;

};



/* hwrm_port_ecn_qstats_input (size:256b/32B) */
@@ -5140,13 +5178,15 @@ struct hwrm_port_clr_stats_output { 
	u8	valid;

};



/* hwrm_port_lpbk_clr_stats_input (size:128b/16B) */

/* hwrm_port_lpbk_clr_stats_input (size:192b/24B) */

struct hwrm_port_lpbk_clr_stats_input {

	__le16	req_type;

	__le16	cmpl_ring;

	__le16	seq_id;

	__le16	target_id;

	__le64	resp_addr;

	__le16	port_id;

	u8	unused_0[6];

};



/* hwrm_port_lpbk_clr_stats_output (size:128b/16B) */
@@ -5291,6 +5331,7 @@ struct hwrm_port_phy_qcaps_output { 
	#define PORT_PHY_QCAPS_RESP_FLAGS2_PFC_UNSUPPORTED             0x2UL

	#define PORT_PHY_QCAPS_RESP_FLAGS2_BANK_ADDR_SUPPORTED         0x4UL

	#define PORT_PHY_QCAPS_RESP_FLAGS2_SPEEDS2_SUPPORTED           0x8UL

	#define PORT_PHY_QCAPS_RESP_FLAGS2_REMOTE_LPBK_UNSUPPORTED     0x10UL

	u8	internal_port_cnt;

	u8	unused_0;

	__le16	supported_speeds2_force_mode;
@@ -9109,6 +9150,7 @@ struct hwrm_struct_hdr { 
	#define STRUCT_HDR_STRUCT_ID_LLDP_GENERIC       0x424UL

	#define STRUCT_HDR_STRUCT_ID_LLDP_DEVICE        0x426UL

	#define STRUCT_HDR_STRUCT_ID_POWER_BKUP         0x427UL

	#define STRUCT_HDR_STRUCT_ID_PEER_MMAP          0x429UL

	#define STRUCT_HDR_STRUCT_ID_AFM_OPAQUE         0x1UL

	#define STRUCT_HDR_STRUCT_ID_PORT_DESCRIPTION   0xaUL

	#define STRUCT_HDR_STRUCT_ID_RSS_V2             0x64UL
@@ -9758,6 +9800,9 @@ struct hwrm_dbg_coredump_initiate_input { 
	__le16	instance;

	__le16	unused_0;

	u8	seg_flags;

	#define DBG_COREDUMP_INITIATE_REQ_SEG_FLAGS_LIVE_DATA                0x1UL

	#define DBG_COREDUMP_INITIATE_REQ_SEG_FLAGS_CRASH_DATA               0x2UL

	#define DBG_COREDUMP_INITIATE_REQ_SEG_FLAGS_COLLECT_CTX_L1_CACHE     0x4UL

	u8	unused_1[7];

};
@@ -10433,13 +10478,13 @@ struct hwrm_selftest_irq_output { 


/* dbc_dbc (size:64b/8B) */

struct dbc_dbc {

	u32	index;

	__le32	index;

	#define DBC_DBC_INDEX_MASK 0xffffffUL

	#define DBC_DBC_INDEX_SFT  0

	#define DBC_DBC_EPOCH      0x1000000UL

	#define DBC_DBC_TOGGLE_MASK 0x6000000UL

	#define DBC_DBC_TOGGLE_SFT 25

	u32	type_path_xid;

	__le32	type_path_xid;

	#define DBC_DBC_XID_MASK          0xfffffUL

	#define DBC_DBC_XID_SFT           0

	#define DBC_DBC_PATH_MASK         0x3000000UL