Commit 3fa56267 authored by Dave Hansen's avatar Dave Hansen
Browse files

x86/cpu: Replace PEBS use of 'x86_cpu_desc' use with 'x86_cpu_id' 



The 'x86_cpu_desc' and 'x86_cpu_id' structures are very similar.
Reduce duplicate infrastructure by moving the few users of
'x86_cpu_desc' to the much more common variant.

The existing X86_MATCH_VFM_STEPS() helper matches ranges of
steppings. Instead of introducing a single-stepping match function
which could get confusing when paired with the range, just use
the stepping min/max match helper and use min==max.

Note that this makes the table more vertically compact because
multiple entries like this:

       INTEL_CPU_DESC(INTEL_SKYLAKE_X,          4, 0x00000000),
       INTEL_CPU_DESC(INTEL_SKYLAKE_X,          5, 0x00000000),
       INTEL_CPU_DESC(INTEL_SKYLAKE_X,          6, 0x00000000),
       INTEL_CPU_DESC(INTEL_SKYLAKE_X,          7, 0x00000000),

can be consolidated down to a single stepping range.

Signed-off-by: default avatarDave Hansen <dave.hansen@linux.intel.com>
Link: https://lore.kernel.org/all/20241213185131.8B610039%40davehans-spike.ostc.intel.com
parent 85b08180

arch/x86/events/intel/core.c

+26 −36
Original line number Diff line number Diff line
@@ -5371,42 +5371,32 @@ static __init void intel_clovertown_quirk(void) 
	x86_pmu.pebs_constraints = NULL;

}



static const struct x86_cpu_desc isolation_ucodes[] = {

	INTEL_CPU_DESC(INTEL_HASWELL,		 3, 0x0000001f),

	INTEL_CPU_DESC(INTEL_HASWELL_L,		 1, 0x0000001e),

	INTEL_CPU_DESC(INTEL_HASWELL_G,		 1, 0x00000015),

	INTEL_CPU_DESC(INTEL_HASWELL_X,		 2, 0x00000037),

	INTEL_CPU_DESC(INTEL_HASWELL_X,		 4, 0x0000000a),

	INTEL_CPU_DESC(INTEL_BROADWELL,		 4, 0x00000023),

	INTEL_CPU_DESC(INTEL_BROADWELL_G,	 1, 0x00000014),

	INTEL_CPU_DESC(INTEL_BROADWELL_D,	 2, 0x00000010),

	INTEL_CPU_DESC(INTEL_BROADWELL_D,	 3, 0x07000009),

	INTEL_CPU_DESC(INTEL_BROADWELL_D,	 4, 0x0f000009),

	INTEL_CPU_DESC(INTEL_BROADWELL_D,	 5, 0x0e000002),

	INTEL_CPU_DESC(INTEL_BROADWELL_X,	 1, 0x0b000014),

	INTEL_CPU_DESC(INTEL_SKYLAKE_X,		 3, 0x00000021),

	INTEL_CPU_DESC(INTEL_SKYLAKE_X,		 4, 0x00000000),

	INTEL_CPU_DESC(INTEL_SKYLAKE_X,		 5, 0x00000000),

	INTEL_CPU_DESC(INTEL_SKYLAKE_X,		 6, 0x00000000),

	INTEL_CPU_DESC(INTEL_SKYLAKE_X,		 7, 0x00000000),

	INTEL_CPU_DESC(INTEL_SKYLAKE_X,		11, 0x00000000),

	INTEL_CPU_DESC(INTEL_SKYLAKE_L,		 3, 0x0000007c),

	INTEL_CPU_DESC(INTEL_SKYLAKE,		 3, 0x0000007c),

	INTEL_CPU_DESC(INTEL_KABYLAKE,		 9, 0x0000004e),

	INTEL_CPU_DESC(INTEL_KABYLAKE_L,	 9, 0x0000004e),

	INTEL_CPU_DESC(INTEL_KABYLAKE_L,	10, 0x0000004e),

	INTEL_CPU_DESC(INTEL_KABYLAKE_L,	11, 0x0000004e),

	INTEL_CPU_DESC(INTEL_KABYLAKE_L,	12, 0x0000004e),

	INTEL_CPU_DESC(INTEL_KABYLAKE,		10, 0x0000004e),

	INTEL_CPU_DESC(INTEL_KABYLAKE,		11, 0x0000004e),

	INTEL_CPU_DESC(INTEL_KABYLAKE,		12, 0x0000004e),

	INTEL_CPU_DESC(INTEL_KABYLAKE,		13, 0x0000004e),

static const struct x86_cpu_id isolation_ucodes[] = {

	X86_MATCH_VFM_STEPS(INTEL_HASWELL,	 3,  3, 0x0000001f),

	X86_MATCH_VFM_STEPS(INTEL_HASWELL_L,	 1,  1, 0x0000001e),

	X86_MATCH_VFM_STEPS(INTEL_HASWELL_G,	 1,  1, 0x00000015),

	X86_MATCH_VFM_STEPS(INTEL_HASWELL_X,	 2,  2, 0x00000037),

	X86_MATCH_VFM_STEPS(INTEL_HASWELL_X,	 4,  4, 0x0000000a),

	X86_MATCH_VFM_STEPS(INTEL_BROADWELL,	 4,  4, 0x00000023),

	X86_MATCH_VFM_STEPS(INTEL_BROADWELL_G,	 1,  1, 0x00000014),

	X86_MATCH_VFM_STEPS(INTEL_BROADWELL_D,	 2,  2, 0x00000010),

	X86_MATCH_VFM_STEPS(INTEL_BROADWELL_D,	 3,  3, 0x07000009),

	X86_MATCH_VFM_STEPS(INTEL_BROADWELL_D,	 4,  4, 0x0f000009),

	X86_MATCH_VFM_STEPS(INTEL_BROADWELL_D,	 5,  5, 0x0e000002),

	X86_MATCH_VFM_STEPS(INTEL_BROADWELL_X,	 1,  1, 0x0b000014),

	X86_MATCH_VFM_STEPS(INTEL_SKYLAKE_X,	 3,  3, 0x00000021),

	X86_MATCH_VFM_STEPS(INTEL_SKYLAKE_X,	 4,  7, 0x00000000),

	X86_MATCH_VFM_STEPS(INTEL_SKYLAKE_X,	11, 11, 0x00000000),

	X86_MATCH_VFM_STEPS(INTEL_SKYLAKE_L,	 3,  3, 0x0000007c),

	X86_MATCH_VFM_STEPS(INTEL_SKYLAKE,	 3,  3, 0x0000007c),

	X86_MATCH_VFM_STEPS(INTEL_KABYLAKE,	 9, 13, 0x0000004e),

	X86_MATCH_VFM_STEPS(INTEL_KABYLAKE_L,	 9, 12, 0x0000004e),

	{}

};



static void intel_check_pebs_isolation(void)

{

	x86_pmu.pebs_no_isolation = !x86_cpu_has_min_microcode_rev(isolation_ucodes);

	x86_pmu.pebs_no_isolation = !x86_match_min_microcode_rev(isolation_ucodes);

}



static __init void intel_pebs_isolation_quirk(void)
@@ -5416,16 +5406,16 @@ static __init void intel_pebs_isolation_quirk(void) 
	intel_check_pebs_isolation();

}



static const struct x86_cpu_desc pebs_ucodes[] = {

	INTEL_CPU_DESC(INTEL_SANDYBRIDGE,	7, 0x00000028),

	INTEL_CPU_DESC(INTEL_SANDYBRIDGE_X,	6, 0x00000618),

	INTEL_CPU_DESC(INTEL_SANDYBRIDGE_X,	7, 0x0000070c),

static const struct x86_cpu_id pebs_ucodes[] = {

	X86_MATCH_VFM_STEPS(INTEL_SANDYBRIDGE,	7, 7, 0x00000028),

	X86_MATCH_VFM_STEPS(INTEL_SANDYBRIDGE_X,	6, 6, 0x00000618),

	X86_MATCH_VFM_STEPS(INTEL_SANDYBRIDGE_X,	7, 7, 0x0000070c),

	{}

};



static bool intel_snb_pebs_broken(void)

{

	return !x86_cpu_has_min_microcode_rev(pebs_ucodes);

	return !x86_match_min_microcode_rev(pebs_ucodes);

}



static void intel_snb_check_microcode(void)