Commit 3fe85618 authored by Suraj Kandpal's avatar Suraj Kandpal Committed by Matt Roper
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drm/i915/xe3lpd: Add new bit range of MAX swing setup 



Add new bit range for Max PHY Swing Setup in PORT_ALPM_CTL
register for DISPLAY_VER >= 30.

v2: implement as two separate macros instead of a single macro
v3: extend previous definition by 2 bits that were previously reserved

Bspec: 70277
Signed-off-by: default avatarSuraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: default avatarMatt Atwood <matthew.s.atwood@intel.com>
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20241018200311.67324-6-matthew.s.atwood@intel.com
parent 2c75bdcc

drivers/gpu/drm/i915/display/intel_psr_regs.h

+1 −1
Original line number Diff line number Diff line
@@ -298,7 +298,7 @@ 
#define _PORT_ALPM_CTL_B			0x16fc2c

#define PORT_ALPM_CTL(port)			_MMIO_PORT(port, _PORT_ALPM_CTL_A, _PORT_ALPM_CTL_B)

#define  PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE	REG_BIT(31)

#define  PORT_ALPM_CTL_MAX_PHY_SWING_SETUP_MASK	REG_GENMASK(23, 20)

#define  PORT_ALPM_CTL_MAX_PHY_SWING_SETUP_MASK	REG_GENMASK(25, 20)

#define  PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(val)	REG_FIELD_PREP(PORT_ALPM_CTL_MAX_PHY_SWING_SETUP_MASK, val)

#define  PORT_ALPM_CTL_MAX_PHY_SWING_HOLD_MASK	REG_GENMASK(19, 16)

#define  PORT_ALPM_CTL_MAX_PHY_SWING_HOLD(val)	REG_FIELD_PREP(PORT_ALPM_CTL_MAX_PHY_SWING_HOLD_MASK, val)