Commit 40a684f9 authored by Vinay Belgaumkar's avatar Vinay Belgaumkar
Browse files

drm/xe: Decouple GuC RC code from xe_guc_pc 



Move enable/disable GuC RC logic into the new file. This will
allow us to independently enable/disable GuC RC and not rely
on SLPC related functions. GuC already provides separate H2G
interfaces to setup GuC RC and SLPC.

Cc: Riana Tauro <riana.tauro@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Reviewed-by: default avatarMichal Wajdeczko <michal.wajdeczko@intel.com>
Reviewed-by: default avatarRiana Tauro <riana.tauro@intel.com>
Signed-off-by: default avatarVinay Belgaumkar <vinay.belgaumkar@intel.com>
Link: https://patch.msgid.link/20260204014234.2867763-2-vinay.belgaumkar@intel.com
parent 10634077

Documentation/gpu/xe/xe_firmware.rst

+3 −0
Original line number Diff line number Diff line
@@ -31,6 +31,9 @@ GuC Power Conservation (PC) 
.. kernel-doc:: drivers/gpu/drm/xe/xe_guc_pc.c

   :doc: GuC Power Conservation (PC)



.. kernel-doc:: drivers/gpu/drm/xe/xe_guc_rc.c

   :doc: GuC Render C-states (GuC RC)



PCIe Gen5 Limitations

=====================

drivers/gpu/drm/xe/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -74,6 +74,7 @@ xe-y += xe_bb.o \ 
	xe_guc_log.o \

	xe_guc_pagefault.o \

	xe_guc_pc.o \

	xe_guc_rc.o \

	xe_guc_submit.o \

	xe_guc_tlb_inval.o \

	xe_heci_gsc.o \

drivers/gpu/drm/xe/xe_gt.c

+0 −1
Original line number Diff line number Diff line
@@ -849,7 +849,6 @@ static void gt_reset_worker(struct work_struct *w) 
	if (IS_SRIOV_PF(gt_to_xe(gt)))

		xe_gt_sriov_pf_stop_prepare(gt);



	xe_uc_gucrc_disable(&gt->uc);

	xe_uc_stop_prepare(&gt->uc);

	xe_pagefault_reset(gt_to_xe(gt), gt);

drivers/gpu/drm/xe/xe_guc.c

+6 −0
Original line number Diff line number Diff line
@@ -35,6 +35,7 @@ 
#include "xe_guc_klv_helpers.h"

#include "xe_guc_log.h"

#include "xe_guc_pc.h"

#include "xe_guc_rc.h"

#include "xe_guc_relay.h"

#include "xe_guc_submit.h"

#include "xe_memirq.h"
@@ -881,6 +882,10 @@ int xe_guc_init_post_hwconfig(struct xe_guc *guc) 
	if (ret)

		return ret;



	ret = xe_guc_rc_init(guc);

	if (ret)

		return ret;



	ret = xe_guc_engine_activity_init(guc);

	if (ret)

		return ret;
@@ -1631,6 +1636,7 @@ void xe_guc_stop_prepare(struct xe_guc *guc) 
	if (!IS_SRIOV_VF(guc_to_xe(guc))) {

		int err;



		xe_guc_rc_disable(guc);

		err = xe_guc_pc_stop(&guc->pc);

		xe_gt_WARN(guc_to_gt(guc), err, "Failed to stop GuC PC: %pe\n",

			   ERR_PTR(err));

drivers/gpu/drm/xe/xe_guc_pc.c

+12 −56
Original line number Diff line number Diff line
@@ -92,6 +92,17 @@ 
 * Render-C states is also a GuC PC feature that is now enabled in Xe for

 * all platforms.

 *

 * Implementation details:

 * -----------------------

 * The implementation for GuC Power Management features is split as follows:

 *

 * xe_guc_rc:  Logic for handling GuC RC

 * xe_gt_idle: Host side logic for RC6 and Coarse Power gating (CPG)

 * xe_guc_pc:  Logic for all other SLPC related features

 *

 * There is some cross interaction between these where host C6 will need to be

 * enabled when we plan to skip GuC RC. Also, the GuC RC mode is currently

 * overridden through 0x3003 which is an SLPC H2G call.

 */



static struct xe_guc *pc_to_guc(struct xe_guc_pc *pc)
@@ -253,22 +264,6 @@ static int pc_action_unset_param(struct xe_guc_pc *pc, u8 id) 
	return ret;

}



static int pc_action_setup_gucrc(struct xe_guc_pc *pc, u32 mode)

{

	struct xe_guc_ct *ct = pc_to_ct(pc);

	u32 action[] = {

		GUC_ACTION_HOST2GUC_SETUP_PC_GUCRC,

		mode,

	};

	int ret;



	ret = xe_guc_ct_send(ct, action, ARRAY_SIZE(action), 0, 0);

	if (ret && !(xe_device_wedged(pc_to_xe(pc)) && ret == -ECANCELED))

		xe_gt_err(pc_to_gt(pc), "GuC RC enable mode=%u failed: %pe\n",

			  mode, ERR_PTR(ret));

	return ret;

}



static u32 decode_freq(u32 raw)

{

	return DIV_ROUND_CLOSEST(raw * GT_FREQUENCY_MULTIPLIER,
@@ -1050,30 +1045,6 @@ int xe_guc_pc_restore_stashed_freq(struct xe_guc_pc *pc) 
	return ret;

}



/**

 * xe_guc_pc_gucrc_disable - Disable GuC RC

 * @pc: Xe_GuC_PC instance

 *

 * Disables GuC RC by taking control of RC6 back from GuC.

 *

 * Return: 0 on success, negative error code on error.

 */

int xe_guc_pc_gucrc_disable(struct xe_guc_pc *pc)

{

	struct xe_device *xe = pc_to_xe(pc);

	struct xe_gt *gt = pc_to_gt(pc);

	int ret = 0;



	if (xe->info.skip_guc_pc)

		return 0;



	ret = pc_action_setup_gucrc(pc, GUCRC_HOST_CONTROL);

	if (ret)

		return ret;



	return xe_gt_idle_disable_c6(gt);

}



/**

 * xe_guc_pc_override_gucrc_mode - override GUCRC mode

 * @pc: Xe_GuC_PC instance
@@ -1247,9 +1218,6 @@ int xe_guc_pc_start(struct xe_guc_pc *pc) 
		return -ETIMEDOUT;



	if (xe->info.skip_guc_pc) {

		if (xe->info.platform != XE_PVC)

			xe_gt_idle_enable_c6(gt);



		/* Request max possible since dynamic freq mgmt is not enabled */

		pc_set_cur_freq(pc, UINT_MAX);

		return 0;
@@ -1291,15 +1259,6 @@ int xe_guc_pc_start(struct xe_guc_pc *pc) 
	if (ret)

		return ret;



	if (xe->info.platform == XE_PVC) {

		xe_guc_pc_gucrc_disable(pc);

		return 0;

	}



	ret = pc_action_setup_gucrc(pc, GUCRC_FIRMWARE_CONTROL);

	if (ret)

		return ret;



	/* Enable SLPC Optimized Strategy for compute */

	ret = pc_action_set_strategy(pc, SLPC_OPTIMIZED_STRATEGY_COMPUTE);
@@ -1319,10 +1278,8 @@ int xe_guc_pc_stop(struct xe_guc_pc *pc) 
{

	struct xe_device *xe = pc_to_xe(pc);



	if (xe->info.skip_guc_pc) {

		xe_gt_idle_disable_c6(pc_to_gt(pc));

	if (xe->info.skip_guc_pc)

		return 0;

	}



	mutex_lock(&pc->freq_lock);

	pc->freq_ready = false;
@@ -1344,7 +1301,6 @@ static void xe_guc_pc_fini_hw(void *arg) 
		return;



	CLASS(xe_force_wake, fw_ref)(gt_to_fw(pc_to_gt(pc)), XE_FORCEWAKE_ALL);

	xe_guc_pc_gucrc_disable(pc);

	XE_WARN_ON(xe_guc_pc_stop(pc));



	/* Bind requested freq to mert_freq_cap before unload */