Commit 40d9c6ea authored by Bjorn Andersson's avatar Bjorn Andersson
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Merge branch... 

Merge branch '20231106-topic-sm8650-upstream-clocks-v3-5-761a6fadb4c0@linaro.org' into arm64-for-6.8

Merge the SM8650 clock bindings, to gain access to the clock constants.
parents 264beb3c 873f2244

Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml

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@@ -35,6 +35,7 @@ properties: 
      - qcom,sm8350-rpmh-clk

      - qcom,sm8450-rpmh-clk

      - qcom,sm8550-rpmh-clk

      - qcom,sm8650-rpmh-clk



  clocks:

    maxItems: 1

Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml

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@@ -17,12 +17,14 @@ description: | 
    include/dt-bindings/clock/qcom,sm8450-gpucc.h

    include/dt-bindings/clock/qcom,sm8550-gpucc.h

    include/dt-bindings/reset/qcom,sm8450-gpucc.h

    include/dt-bindings/reset/qcom,sm8650-gpucc.h



properties:

  compatible:

    enum:

      - qcom,sm8450-gpucc

      - qcom,sm8550-gpucc

      - qcom,sm8650-gpucc



  clocks:

    items:

Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml

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@@ -13,12 +13,16 @@ description: | 
  Qualcomm TCSR clock control module provides the clocks, resets and

  power domains on SM8550



  See also:: include/dt-bindings/clock/qcom,sm8550-tcsr.h

  See also:

  - include/dt-bindings/clock/qcom,sm8550-tcsr.h

  - include/dt-bindings/clock/qcom,sm8650-tcsr.h



properties:

  compatible:

    items:

      - const: qcom,sm8550-tcsr

      - enum:

          - qcom,sm8550-tcsr

          - qcom,sm8650-tcsr

      - const: syscon



  clocks:

Documentation/devicetree/bindings/clock/qcom,sm8650-dispcc.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/qcom,sm8650-dispcc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm Display Clock & Reset Controller for SM8650



maintainers:

  - Bjorn Andersson <andersson@kernel.org>

  - Neil Armstrong <neil.armstrong@linaro.org>



description: |

  Qualcomm display clock control module provides the clocks, resets and power

  domains on SM8650.



  See also:: include/dt-bindings/clock/qcom,sm8650-dispcc.h



properties:

  compatible:

    enum:

      - qcom,sm8650-dispcc



  clocks:

    items:

      - description: Board XO source

      - description: Board Always On XO source

      - description: Display's AHB clock

      - description: sleep clock

      - description: Byte clock from DSI PHY0

      - description: Pixel clock from DSI PHY0

      - description: Byte clock from DSI PHY1

      - description: Pixel clock from DSI PHY1

      - description: Link clock from DP PHY0

      - description: VCO DIV clock from DP PHY0

      - description: Link clock from DP PHY1

      - description: VCO DIV clock from DP PHY1

      - description: Link clock from DP PHY2

      - description: VCO DIV clock from DP PHY2

      - description: Link clock from DP PHY3

      - description: VCO DIV clock from DP PHY3



  '#clock-cells':

    const: 1



  '#reset-cells':

    const: 1



  '#power-domain-cells':

    const: 1



  reg:

    maxItems: 1



  power-domains:

    description:

      A phandle and PM domain specifier for the MMCX power domain.

    maxItems: 1



  required-opps:

    description:

      A phandle to an OPP node describing required MMCX performance point.

    maxItems: 1



required:

  - compatible

  - reg

  - clocks

  - '#clock-cells'

  - '#reset-cells'

  - '#power-domain-cells'



additionalProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,sm8650-gcc.h>

    #include <dt-bindings/clock/qcom,rpmh.h>

    #include <dt-bindings/power/qcom-rpmpd.h>

    #include <dt-bindings/power/qcom,rpmhpd.h>

    clock-controller@af00000 {

      compatible = "qcom,sm8650-dispcc";

      reg = <0x0af00000 0x10000>;

      clocks = <&rpmhcc RPMH_CXO_CLK>,

               <&rpmhcc RPMH_CXO_CLK_A>,

               <&gcc GCC_DISP_AHB_CLK>,

               <&sleep_clk>,

               <&dsi0_phy 0>,

               <&dsi0_phy 1>,

               <&dsi1_phy 0>,

               <&dsi1_phy 1>,

               <&dp0_phy 0>,

               <&dp0_phy 1>,

               <&dp1_phy 0>,

               <&dp1_phy 1>,

               <&dp2_phy 0>,

               <&dp2_phy 1>,

               <&dp3_phy 0>,

               <&dp3_phy 1>;

      #clock-cells = <1>;

      #reset-cells = <1>;

      #power-domain-cells = <1>;

      power-domains = <&rpmhpd RPMHPD_MMCX>;

      required-opps = <&rpmhpd_opp_low_svs>;

    };

...

Documentation/devicetree/bindings/clock/qcom,sm8650-gcc.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

%YAML 1.2

---

$id: http://devicetree.org/schemas/clock/qcom,sm8650-gcc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Qualcomm Global Clock & Reset Controller on SM8650



maintainers:

  - Bjorn Andersson <andersson@kernel.org>



description: |

  Qualcomm global clock control module provides the clocks, resets and power

  domains on SM8650



  See also:: include/dt-bindings/clock/qcom,sm8650-gcc.h



properties:

  compatible:

    const: qcom,sm8650-gcc



  clocks:

    items:

      - description: Board XO source

      - description: Board Always On XO source

      - description: Sleep clock source

      - description: PCIE 0 Pipe clock source

      - description: PCIE 1 Pipe clock source

      - description: PCIE 1 Phy Auxiliary clock source

      - description: UFS Phy Rx symbol 0 clock source

      - description: UFS Phy Rx symbol 1 clock source

      - description: UFS Phy Tx symbol 0 clock source

      - description: USB3 Phy wrapper pipe clock source



required:

  - compatible

  - clocks



allOf:

  - $ref: qcom,gcc.yaml#



unevaluatedProperties: false



examples:

  - |

    #include <dt-bindings/clock/qcom,rpmh.h>

    clock-controller@100000 {

      compatible = "qcom,sm8650-gcc";

      reg = <0x00100000 0x001f4200>;

      clocks = <&rpmhcc RPMH_CXO_CLK>,

               <&rpmhcc RPMH_CXO_CLK_A>,

               <&sleep_clk>,

               <&pcie0_phy>,

               <&pcie1_phy>,

               <&pcie_1_phy_aux_clk>,

               <&ufs_mem_phy 0>,

               <&ufs_mem_phy 1>,

               <&ufs_mem_phy 2>,

               <&usb_1_qmpphy>;

      #clock-cells = <1>;

      #reset-cells = <1>;

      #power-domain-cells = <1>;

    };



...