Commit 426b8442 authored Jan 27, 2026 by Ian Rogers Committed by Arnaldo Carvalho de Melo Jan 28, 2026

perf jevents: Add Miss Level Parallelism (MLP) metric for Intel



Number of outstanding load misses per cycle.

Signed-off-by: Ian Rogers <irogers@google.com>
Tested-by: Thomas Falcon <thomas.falcon@intel.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Benjamin Gray <bgray@linux.ibm.com>
Cc: Caleb Biggers <caleb.biggers@intel.com>
Cc: Edward Baker <edward.baker@intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@linaro.org>
Cc: Jing Zhang <renyu.zj@linux.alibaba.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.g.garry@oracle.com>
Cc: Leo Yan <leo.yan@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Perry Taylor <perry.taylor@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Sandipan Das <sandipan.das@amd.com>
Cc: Weilin Wang <weilin.wang@intel.com>
Cc: Xu Yang <xu.yang_2@nxp.com>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>

parent d666f017

tools/perf/pmu-events/intel_metrics.py

+15 −0

Original line number	Diff line number	Diff line
		@@ -624,6 +624,20 @@ def IntelL2() -> Optional[MetricGroup]:
		], description="L2 data cache analysis")


		def IntelMlp() -> Optional[Metric]:
		try:
		l1d = Event("L1D_PEND_MISS.PENDING")
		l1dc = Event("L1D_PEND_MISS.PENDING_CYCLES")
		except:
		return None

		l1dc = Select(l1dc / 2, Literal("#smt_on"), l1dc)
		ml = d_ratio(l1d, l1dc)
		return Metric("lpm_mlp",
		"Miss level parallelism - number of outstanding load misses per cycle (higher is better)",
		ml, "load_miss_pending/cycle")


		def IntelPorts() -> Optional[MetricGroup]:
		pipeline_events = json.load(
		open(f"{_args.events_path}/x86/{_args.model}/pipeline.json"))
		@@ -836,6 +850,7 @@ def main() -> None:
		IntelIlp(),
		IntelL2(),
		IntelLdSt(),
		IntelMlp(),
		IntelPorts(),
		IntelSwpf(),
		])