Commit 42b9fed3 authored by Anshuman Khandual's avatar Anshuman Khandual Committed by Catalin Marinas
Browse files

KVM: arm64: Replace custom macros with fields from ID_AA64PFR0_EL1 



This replaces custom macros usage (i.e ID_AA64PFR0_EL1_ELx_64BIT_ONLY and
ID_AA64PFR0_EL1_ELx_32BIT_64BIT) and instead directly uses register fields
from ID_AA64PFR0_EL1 sysreg definition.

Cc: Marc Zyngier <maz@kernel.org>
Cc: Oliver Upton <oliver.upton@linux.dev>
Cc: Will Deacon <will@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: kvmarm@lists.linux.dev
Cc: linux-kernel@vger.kernel.org
Signed-off-by: default avatarAnshuman Khandual <anshuman.khandual@arm.com>
Acked-by: default avatarMarc Zyngier <maz@kernel.org>
Acked-by: default avatarMark Rutland <mark.rutland@arm.com>
Link: https://lore.kernel.org/r/20240613102710.3295108-2-anshuman.khandual@arm.com


Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent e8cde32f

arch/arm64/kvm/hyp/include/nvhe/fixed_config.h

+5 −5
Original line number Diff line number Diff line
@@ -52,11 +52,11 @@ 
 *	Supported by KVM

 */

#define PVM_ID_AA64PFR0_RESTRICT_UNSIGNED (\

	FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL0), ID_AA64PFR0_EL1_ELx_64BIT_ONLY) | \

	FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL1), ID_AA64PFR0_EL1_ELx_64BIT_ONLY) | \

	FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL2), ID_AA64PFR0_EL1_ELx_64BIT_ONLY) | \

	FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL3), ID_AA64PFR0_EL1_ELx_64BIT_ONLY) | \

	FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_RAS), ID_AA64PFR0_EL1_RAS_IMP) \

	SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, EL0, IMP) | \

	SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, EL1, IMP) | \

	SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, EL2, IMP) | \

	SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, EL3, IMP) | \

	SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, RAS, IMP) \

	)



/*

arch/arm64/kvm/hyp/nvhe/pkvm.c

+2 −2
Original line number Diff line number Diff line
@@ -33,9 +33,9 @@ static void pvm_init_traps_aa64pfr0(struct kvm_vcpu *vcpu) 


	/* Protected KVM does not support AArch32 guests. */

	BUILD_BUG_ON(FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL0),

		PVM_ID_AA64PFR0_RESTRICT_UNSIGNED) != ID_AA64PFR0_EL1_ELx_64BIT_ONLY);

		PVM_ID_AA64PFR0_RESTRICT_UNSIGNED) != ID_AA64PFR0_EL1_EL0_IMP);

	BUILD_BUG_ON(FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL1),

		PVM_ID_AA64PFR0_RESTRICT_UNSIGNED) != ID_AA64PFR0_EL1_ELx_64BIT_ONLY);

		PVM_ID_AA64PFR0_RESTRICT_UNSIGNED) != ID_AA64PFR0_EL1_EL1_IMP);



	/*

	 * Linux guests assume support for floating-point and Advanced SIMD. Do

arch/arm64/kvm/hyp/nvhe/sys_regs.c

+1 −1
Original line number Diff line number Diff line
@@ -276,7 +276,7 @@ static bool pvm_access_id_aarch32(struct kvm_vcpu *vcpu, 
	 * of AArch32 feature id registers.

	 */

	BUILD_BUG_ON(FIELD_GET(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL1),

		     PVM_ID_AA64PFR0_RESTRICT_UNSIGNED) > ID_AA64PFR0_EL1_ELx_64BIT_ONLY);

		     PVM_ID_AA64PFR0_RESTRICT_UNSIGNED) > ID_AA64PFR0_EL1_EL1_IMP);



	return pvm_access_raz_wi(vcpu, p, r);

}