Commit 430e2978 authored by Hari Nagalla's avatar Hari Nagalla Committed by Mathieu Poirier
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dt-bindings: remoteproc: k3-dsp: Correct optional sram properties for AM62A SoCs



The C7xv-dsp on AM62A have 32KB L1 I-cache and a 64KB L1 D-cache. It
does not have an addressable l1dram . So, remove this optional sram
property from the bindings to fix device tree build warnings.

Signed-off-by: default avatarHari Nagalla <hnagalla@ti.com>
Reviewed-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240604171450.2455-1-hnagalla@ti.com


Signed-off-by: default avatarMathieu Poirier <mathieu.poirier@linaro.org>
parent 568b13b6
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+51 −38
Original line number Diff line number Diff line
@@ -25,9 +25,6 @@ description: |
  host processor (Arm CorePac) to perform the device management of the remote
  processor and to communicate with the remote processor.

allOf:
  - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#

properties:
  compatible:
    enum:
@@ -89,7 +86,8 @@ properties:
      should be defined as per the generic bindings in,
      Documentation/devicetree/bindings/sram/sram.yaml

if:
allOf:
  - if:
      properties:
        compatible:
          enum:
@@ -106,12 +104,11 @@ then:
            - const: l2sram
            - const: l1pram
            - const: l1dram
else:
  if:

  - if:
      properties:
        compatible:
          enum:
          - ti,am62a-c7xv-dsp
            - ti,j721e-c71-dsp
            - ti,j721s2-c71-dsp
    then:
@@ -125,6 +122,22 @@ else:
            - const: l2sram
            - const: l1dram

  - if:
      properties:
        compatible:
          enum:
            - ti,am62a-c7xv-dsp
    then:
      properties:
        reg:
          items:
            - description: Address and Size of the L2 SRAM internal memory region
        reg-names:
          items:
            - const: l2sram

  - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#

required:
  - compatible
  - reg