Commit 435db526 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Evade transcoder's vblank when doing seamless M/N changes 



The transcoder M/N values are double buffered on the transcoder's
undelayed vblank. So when doing seamless M/N fastsets we need to
evade also that.

Note that currently the pipe's delayed vblank == transcoder's
undelayed vblank, so this is still a nop change. But in the
future when we may have to delay the pipe's vblank to create
a register programming window ("window2") for the DSB.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230404175431.23064-2-ville.syrjala@linux.intel.com


Reviewed-by: default avatarMitul Golani <mitulkumar.ajitkumar.golani@intel.com>
parent a2da6702

drivers/gpu/drm/i915/display/intel_crtc.c

+7 −0
Original line number Diff line number Diff line
@@ -510,6 +510,13 @@ void intel_pipe_update_start(struct intel_crtc_state *new_crtc_state) 
						      VBLANK_EVASION_TIME_US);

	max = vblank_start - 1;



	/*

	 * M/N is double buffered on the transcoder's undelayed vblank,

	 * so with seamless M/N we must evade both vblanks.

	 */

	if (new_crtc_state->seamless_m_n && intel_crtc_needs_fastset(new_crtc_state))

		min -= adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay;



	if (min <= 0 || max <= 0)

		goto irq_disable;