Unverified Commit 437c99c2 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'riscv-dt-fixes-for-v6.7-rc4' of... 

Merge tag 'riscv-dt-fixes-for-v6.7-rc4' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux

 into arm/fixes

RISC-V Devicetree fixes for v6.7-rc4

Two fixes, both rather minor. The first fixes some dtbs_check warnings
introduced after an update to the bindings, that returns the
architecture to being clean of dtbs_check issues. The second relocates
a soc-specific property to the appropriate location in $soc.dtsi, and
hopefully avoids the same mistake being copy-pasted into more
devicetrees.

Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>

* tag 'riscv-dt-fixes-for-v6.7-rc4' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
  riscv: dts: microchip: move timebase-frequency to mpfs.dtsi
  riscv: dts: sophgo: remove address-cells from intc node

Link: https://lore.kernel.org/r/20231130-maternity-majestic-dd29f0170050@spud


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 1133ae11 79997eda

arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts

+0 −7
Original line number Diff line number Diff line
@@ -8,9 +8,6 @@ 
#include <dt-bindings/gpio/gpio.h>

#include <dt-bindings/leds/common.h>



/* Clock frequency (in Hz) of the rtcclk */

#define RTCCLK_FREQ		1000000



/ {

	model = "Microchip PolarFire-SoC Icicle Kit";

	compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit",
@@ -29,10 +26,6 @@ chosen { 
		stdout-path = "serial1:115200n8";

	};



	cpus {

		timebase-frequency = <RTCCLK_FREQ>;

	};



	leds {

		compatible = "gpio-leds";

arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dts

+0 −7
Original line number Diff line number Diff line
@@ -10,9 +10,6 @@ 
#include "mpfs.dtsi"

#include "mpfs-m100pfs-fabric.dtsi"



/* Clock frequency (in Hz) of the rtcclk */

#define MTIMER_FREQ	1000000



/ {

	model = "Aries Embedded M100PFEVPS";

	compatible = "aries,m100pfsevp", "microchip,mpfs";
@@ -33,10 +30,6 @@ chosen { 
		stdout-path = "serial1:115200n8";

	};



	cpus {

		timebase-frequency = <MTIMER_FREQ>;

	};



	ddrc_cache_lo: memory@80000000 {

		device_type = "memory";

		reg = <0x0 0x80000000 0x0 0x40000000>;

arch/riscv/boot/dts/microchip/mpfs-polarberry.dts

+0 −7
Original line number Diff line number Diff line
@@ -6,9 +6,6 @@ 
#include "mpfs.dtsi"

#include "mpfs-polarberry-fabric.dtsi"



/* Clock frequency (in Hz) of the rtcclk */

#define MTIMER_FREQ	1000000



/ {

	model = "Sundance PolarBerry";

	compatible = "sundance,polarberry", "microchip,mpfs";
@@ -22,10 +19,6 @@ chosen { 
		stdout-path = "serial0:115200n8";

	};



	cpus {

		timebase-frequency = <MTIMER_FREQ>;

	};



	ddrc_cache_lo: memory@80000000 {

		device_type = "memory";

		reg = <0x0 0x80000000 0x0 0x2e000000>;

arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts

+0 −7
Original line number Diff line number Diff line
@@ -6,9 +6,6 @@ 
#include "mpfs.dtsi"

#include "mpfs-sev-kit-fabric.dtsi"



/* Clock frequency (in Hz) of the rtcclk */

#define MTIMER_FREQ		1000000



/ {

	#address-cells = <2>;

	#size-cells = <2>;
@@ -28,10 +25,6 @@ chosen { 
		stdout-path = "serial1:115200n8";

	};



	cpus {

		timebase-frequency = <MTIMER_FREQ>;

	};



	reserved-memory {

		#address-cells = <2>;

		#size-cells = <2>;

arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts

+0 −7
Original line number Diff line number Diff line
@@ -11,9 +11,6 @@ 
#include "mpfs.dtsi"

#include "mpfs-tysom-m-fabric.dtsi"



/* Clock frequency (in Hz) of the rtcclk */

#define MTIMER_FREQ		1000000



/ {

	model = "Aldec TySOM-M-MPFS250T-REV2";

	compatible = "aldec,tysom-m-mpfs250t-rev2", "microchip,mpfs";
@@ -34,10 +31,6 @@ chosen { 
		stdout-path = "serial1:115200n8";

	};



	cpus {

		timebase-frequency = <MTIMER_FREQ>;

	};



	ddrc_cache_lo: memory@80000000 {

		device_type = "memory";

		reg = <0x0 0x80000000 0x0 0x30000000>;