Commit 44019387 authored by Lad Prabhakar's avatar Lad Prabhakar Committed by Geert Uytterhoeven
Browse files

clk: renesas: r9a07g043: Add clock and reset entry for PLIC 



Add the missing clock and reset entry for PLIC. Also add
R9A07G043_NCEPLIC_ACLK to the critical clocks list.

Fixes: 95d48d27 ("clk: renesas: r9a07g043: Add support for RZ/Five SoC")
Signed-off-by: default avatarLad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20240403200952.633084-1-prabhakar.mahadev-lad.rj@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent ef9916d0

drivers/clk/renesas/r9a07g043-cpg.c

+9 −0
Original line number Diff line number Diff line
@@ -280,6 +280,10 @@ static const struct rzg2l_mod_clk r9a07g043_mod_clks[] = { 
				0x5a8, 1),

	DEF_MOD("tsu_pclk",	R9A07G043_TSU_PCLK, R9A07G043_CLK_TSU,

				0x5ac, 0),

#ifdef CONFIG_RISCV

	DEF_MOD("nceplic_aclk",	R9A07G043_NCEPLIC_ACLK, R9A07G043_CLK_P1,

				0x608, 0),

#endif

};



static const struct rzg2l_reset r9a07g043_resets[] = {
@@ -338,6 +342,10 @@ static const struct rzg2l_reset r9a07g043_resets[] = { 
	DEF_RST(R9A07G043_ADC_PRESETN, 0x8a8, 0),

	DEF_RST(R9A07G043_ADC_ADRST_N, 0x8a8, 1),

	DEF_RST(R9A07G043_TSU_PRESETN, 0x8ac, 0),

#ifdef CONFIG_RISCV

	DEF_RST(R9A07G043_NCEPLIC_ARESETN, 0x908, 0),

#endif



};



static const unsigned int r9a07g043_crit_mod_clks[] __initconst = {
@@ -347,6 +355,7 @@ static const unsigned int r9a07g043_crit_mod_clks[] __initconst = { 
#endif

#ifdef CONFIG_RISCV

	MOD_CLK_BASE + R9A07G043_IAX45_CLK,

	MOD_CLK_BASE + R9A07G043_NCEPLIC_ACLK,

#endif

	MOD_CLK_BASE + R9A07G043_DMAC_ACLK,

};