Unverified Commit 442ece6b authored by Mark Brown's avatar Mark Brown
Browse files

ASoC: SOF: Intel: add LunarLake support 

Merge series from Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>:

This patchset first fixes a number of errors made in the hda-mlink
support, then adds Lunar Lake definitions. The main contribution is
the hda-dai changes where the HDaudio DMA is now used for SSP, DMIC
and SoundWire. In previous hardware the GPDMA (aka DesignWare) was
used and controlled by the audio firmware. The volume of code is
minimized with the abstraction added in previous kernel cycles.

Due to cross-dependencies between ASoC and SoundWire trees, the full
support for jack detection will be deferred to the next kernel
cycle. There's not much point to ask for a sync of the two trees to
support one patch for each tree - we are at -rc5 already.
parents 93fd2be6 02c7f872

include/linux/pci_ids.h

+90 −16
Original line number Diff line number Diff line
@@ -2644,6 +2644,7 @@ 


#define PCI_VENDOR_ID_INTEL		0x8086

#define PCI_DEVICE_ID_INTEL_EESSC	0x0008

#define PCI_DEVICE_ID_INTEL_HDA_CML_LP	0x02c8

#define PCI_DEVICE_ID_INTEL_PXHD_0	0x0320

#define PCI_DEVICE_ID_INTEL_PXHD_1	0x0321

#define PCI_DEVICE_ID_INTEL_PXH_0	0x0329
@@ -2659,8 +2660,10 @@ 
#define PCI_DEVICE_ID_INTEL_82424	0x0483

#define PCI_DEVICE_ID_INTEL_82378	0x0484

#define PCI_DEVICE_ID_INTEL_82425	0x0486

#define PCI_DEVICE_ID_INTEL_HDA_CML_H	0x06c8

#define PCI_DEVICE_ID_INTEL_MRST_SD0	0x0807

#define PCI_DEVICE_ID_INTEL_MRST_SD1	0x0808

#define PCI_DEVICE_ID_INTEL_HDA_OAKTRAIL	0x080a

#define PCI_DEVICE_ID_INTEL_MFD_SD	0x0820

#define PCI_DEVICE_ID_INTEL_MFD_SDIO1	0x0821

#define PCI_DEVICE_ID_INTEL_MFD_SDIO2	0x0822
@@ -2670,15 +2673,19 @@ 
#define PCI_DEVICE_ID_INTEL_QUARK_X1000_ILB	0x095e

#define PCI_DEVICE_ID_INTEL_I960	0x0960

#define PCI_DEVICE_ID_INTEL_I960RM	0x0962

#define PCI_DEVICE_ID_INTEL_HDA_HSW_0	0x0a0c

#define PCI_DEVICE_ID_INTEL_HDA_HSW_2	0x0c0c

#define PCI_DEVICE_ID_INTEL_CENTERTON_ILB	0x0c60

#define PCI_DEVICE_ID_INTEL_HDA_HSW_3	0x0d0c

#define PCI_DEVICE_ID_INTEL_HDA_BYT	0x0f04

#define PCI_DEVICE_ID_INTEL_SST_BYT	0x0f28

#define PCI_DEVICE_ID_INTEL_8257X_SOL	0x1062

#define PCI_DEVICE_ID_INTEL_82573E_SOL	0x1085

#define PCI_DEVICE_ID_INTEL_82573L_SOL	0x108f

#define PCI_DEVICE_ID_INTEL_82815_MC	0x1130

#define PCI_DEVICE_ID_INTEL_82815_CGC	0x1132

#define PCI_DEVICE_ID_INTEL_SST_TNG	0x119a

#define PCI_DEVICE_ID_INTEL_82092AA_0	0x1221

#define PCI_DEVICE_ID_INTEL_7505_0	0x2550

#define PCI_DEVICE_ID_INTEL_7205_0	0x255d

#define PCI_DEVICE_ID_INTEL_82437	0x122d

#define PCI_DEVICE_ID_INTEL_82371FB_0	0x122e

#define PCI_DEVICE_ID_INTEL_82371FB_1	0x1230
@@ -2704,20 +2711,26 @@ 
#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_BRIDGE  0x1576

#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_NHI     0x1577

#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_BRIDGE  0x1578

#define PCI_DEVICE_ID_INTEL_HDA_BDW	0x160c

#define PCI_DEVICE_ID_INTEL_80960_RP	0x1960

#define PCI_DEVICE_ID_INTEL_QAT_C3XXX	0x19e2

#define PCI_DEVICE_ID_INTEL_QAT_C3XXX_VF	0x19e3

#define PCI_DEVICE_ID_INTEL_82840_HB	0x1a21

#define PCI_DEVICE_ID_INTEL_82845_HB	0x1a30

#define PCI_DEVICE_ID_INTEL_IOAT	0x1a38

#define PCI_DEVICE_ID_INTEL_HDA_CPT	0x1c20

#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN	0x1c41

#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX	0x1c5f

#define PCI_DEVICE_ID_INTEL_HDA_PBG	0x1d20

#define PCI_DEVICE_ID_INTEL_PATSBURG_LPC_0	0x1d40

#define PCI_DEVICE_ID_INTEL_PATSBURG_LPC_1	0x1d41

#define PCI_DEVICE_ID_INTEL_HDA_PPT	0x1e20

#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI	0x1e31

#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN	0x1e40

#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX	0x1e5f

#define PCI_DEVICE_ID_INTEL_VMD_201D	0x201d

#define PCI_DEVICE_ID_INTEL_HDA_BSW	0x2284

#define PCI_DEVICE_ID_INTEL_SST_BSW	0x22a8

#define PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MIN	0x2310

#define PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MAX	0x231f

#define PCI_DEVICE_ID_INTEL_82801AA_0	0x2410
@@ -2772,6 +2785,8 @@ 
#define PCI_DEVICE_ID_INTEL_82850_HB	0x2530

#define PCI_DEVICE_ID_INTEL_82860_HB	0x2531

#define PCI_DEVICE_ID_INTEL_E7501_MCH	0x254c

#define PCI_DEVICE_ID_INTEL_7505_0	0x2550

#define PCI_DEVICE_ID_INTEL_7205_0	0x255d

#define PCI_DEVICE_ID_INTEL_82845G_HB	0x2560

#define PCI_DEVICE_ID_INTEL_82845G_IG	0x2562

#define PCI_DEVICE_ID_INTEL_82865_HB	0x2570
@@ -2793,12 +2808,14 @@ 
#define PCI_DEVICE_ID_INTEL_ICH6_0	0x2640

#define PCI_DEVICE_ID_INTEL_ICH6_1	0x2641

#define PCI_DEVICE_ID_INTEL_ICH6_2	0x2642

#define PCI_DEVICE_ID_INTEL_HDA_ICH6	0x2668

#define PCI_DEVICE_ID_INTEL_ICH6_16	0x266a

#define PCI_DEVICE_ID_INTEL_ICH6_17	0x266d

#define PCI_DEVICE_ID_INTEL_ICH6_18	0x266e

#define PCI_DEVICE_ID_INTEL_ICH6_19	0x266f

#define PCI_DEVICE_ID_INTEL_ESB2_0	0x2670

#define PCI_DEVICE_ID_INTEL_ESB2_14	0x2698

#define PCI_DEVICE_ID_INTEL_HDA_ESB2	0x269a

#define PCI_DEVICE_ID_INTEL_ESB2_17	0x269b

#define PCI_DEVICE_ID_INTEL_ESB2_18	0x269e

#define PCI_DEVICE_ID_INTEL_82945G_HB	0x2770
@@ -2806,11 +2823,12 @@ 
#define PCI_DEVICE_ID_INTEL_3000_HB	0x2778

#define PCI_DEVICE_ID_INTEL_82945GM_HB	0x27a0

#define PCI_DEVICE_ID_INTEL_82945GM_IG	0x27a2

#define PCI_DEVICE_ID_INTEL_ICH7_30	0x27b0

#define PCI_DEVICE_ID_INTEL_ICH7_0	0x27b8

#define PCI_DEVICE_ID_INTEL_ICH7_1	0x27b9

#define PCI_DEVICE_ID_INTEL_ICH7_30	0x27b0

#define PCI_DEVICE_ID_INTEL_TGP_LPC	0x27bc

#define PCI_DEVICE_ID_INTEL_ICH7_31	0x27bd

#define PCI_DEVICE_ID_INTEL_HDA_ICH7	0x27d8

#define PCI_DEVICE_ID_INTEL_ICH7_17	0x27da

#define PCI_DEVICE_ID_INTEL_ICH7_19	0x27dd

#define PCI_DEVICE_ID_INTEL_ICH7_20	0x27de
@@ -2821,17 +2839,20 @@ 
#define PCI_DEVICE_ID_INTEL_ICH8_3	0x2814

#define PCI_DEVICE_ID_INTEL_ICH8_4	0x2815

#define PCI_DEVICE_ID_INTEL_ICH8_5	0x283e

#define PCI_DEVICE_ID_INTEL_HDA_ICH8	0x284b

#define PCI_DEVICE_ID_INTEL_ICH8_6	0x2850

#define PCI_DEVICE_ID_INTEL_VMD_28C0	0x28c0

#define PCI_DEVICE_ID_INTEL_ICH9_0	0x2910

#define PCI_DEVICE_ID_INTEL_ICH9_1	0x2917

#define PCI_DEVICE_ID_INTEL_ICH9_2	0x2912

#define PCI_DEVICE_ID_INTEL_ICH9_3	0x2913

#define PCI_DEVICE_ID_INTEL_ICH9_4	0x2914

#define PCI_DEVICE_ID_INTEL_ICH9_5	0x2919

#define PCI_DEVICE_ID_INTEL_ICH9_6	0x2930

#define PCI_DEVICE_ID_INTEL_ICH9_7	0x2916

#define PCI_DEVICE_ID_INTEL_ICH9_1	0x2917

#define PCI_DEVICE_ID_INTEL_ICH9_8	0x2918

#define PCI_DEVICE_ID_INTEL_ICH9_5	0x2919

#define PCI_DEVICE_ID_INTEL_ICH9_6	0x2930

#define PCI_DEVICE_ID_INTEL_HDA_ICH9_0	0x293e

#define PCI_DEVICE_ID_INTEL_HDA_ICH9_1	0x293f

#define PCI_DEVICE_ID_INTEL_I7_MCR	0x2c18

#define PCI_DEVICE_ID_INTEL_I7_MC_TAD	0x2c19

#define PCI_DEVICE_ID_INTEL_I7_MC_RAS	0x2c1a
@@ -2848,8 +2869,8 @@ 
#define PCI_DEVICE_ID_INTEL_I7_MC_CH2_ADDR  0x2c31

#define PCI_DEVICE_ID_INTEL_I7_MC_CH2_RANK  0x2c32

#define PCI_DEVICE_ID_INTEL_I7_MC_CH2_TC    0x2c33

#define PCI_DEVICE_ID_INTEL_I7_NONCORE	0x2c41

#define PCI_DEVICE_ID_INTEL_I7_NONCORE_ALT 0x2c40

#define PCI_DEVICE_ID_INTEL_I7_NONCORE	0x2c41

#define PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE     0x2c50

#define PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_ALT 0x2c51

#define PCI_DEVICE_ID_INTEL_LYNNFIELD_NONCORE_REV2 0x2c70
@@ -2883,6 +2904,7 @@ 
#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_ADDR_REV2  0x2db1

#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_RANK_REV2  0x2db2

#define PCI_DEVICE_ID_INTEL_LYNNFIELD_MC_CH2_TC_REV2    0x2db3

#define PCI_DEVICE_ID_INTEL_HDA_GML	0x3198

#define PCI_DEVICE_ID_INTEL_82855PM_HB	0x3340

#define PCI_DEVICE_ID_INTEL_IOAT_TBG4	0x3429

#define PCI_DEVICE_ID_INTEL_IOAT_TBG5	0x342a
@@ -2893,12 +2915,13 @@ 
#define PCI_DEVICE_ID_INTEL_IOAT_TBG1	0x3431

#define PCI_DEVICE_ID_INTEL_IOAT_TBG2	0x3432

#define PCI_DEVICE_ID_INTEL_IOAT_TBG3	0x3433

#define PCI_DEVICE_ID_INTEL_HDA_ICL_LP	0x34c8

#define PCI_DEVICE_ID_INTEL_82830_HB	0x3575

#define PCI_DEVICE_ID_INTEL_82830_CGC	0x3577

#define PCI_DEVICE_ID_INTEL_82854_HB	0x358c

#define PCI_DEVICE_ID_INTEL_82854_IG	0x358e

#define PCI_DEVICE_ID_INTEL_82855GM_HB	0x3580

#define PCI_DEVICE_ID_INTEL_82855GM_IG	0x3582

#define PCI_DEVICE_ID_INTEL_82854_HB	0x358c

#define PCI_DEVICE_ID_INTEL_82854_IG	0x358e

#define PCI_DEVICE_ID_INTEL_E7520_MCH	0x3590

#define PCI_DEVICE_ID_INTEL_E7320_MCH	0x3592

#define PCI_DEVICE_ID_INTEL_MCH_PA	0x3595
@@ -2908,11 +2931,11 @@ 
#define PCI_DEVICE_ID_INTEL_MCH_PC	0x3599

#define PCI_DEVICE_ID_INTEL_MCH_PC1	0x359a

#define PCI_DEVICE_ID_INTEL_E7525_MCH	0x359e

#define PCI_DEVICE_ID_INTEL_IOAT_CNB	0x360b

#define PCI_DEVICE_ID_INTEL_FBD_CNB	0x360c

#define PCI_DEVICE_ID_INTEL_I7300_MCH_ERR 0x360c

#define PCI_DEVICE_ID_INTEL_I7300_MCH_FB0 0x360f

#define PCI_DEVICE_ID_INTEL_I7300_MCH_FB1 0x3610

#define PCI_DEVICE_ID_INTEL_IOAT_CNB	0x360b

#define PCI_DEVICE_ID_INTEL_FBD_CNB	0x360c

#define PCI_DEVICE_ID_INTEL_IOAT_JSF0	0x3710

#define PCI_DEVICE_ID_INTEL_IOAT_JSF1	0x3711

#define PCI_DEVICE_ID_INTEL_IOAT_JSF2	0x3712
@@ -2925,14 +2948,19 @@ 
#define PCI_DEVICE_ID_INTEL_IOAT_JSF9	0x3719

#define PCI_DEVICE_ID_INTEL_QAT_C62X	0x37c8

#define PCI_DEVICE_ID_INTEL_QAT_C62X_VF	0x37c9

#define PCI_DEVICE_ID_INTEL_HDA_ICL_N	0x38c8

#define PCI_DEVICE_ID_INTEL_ICH10_0	0x3a14

#define PCI_DEVICE_ID_INTEL_ICH10_1	0x3a16

#define PCI_DEVICE_ID_INTEL_ICH10_2	0x3a18

#define PCI_DEVICE_ID_INTEL_ICH10_3	0x3a1a

#define PCI_DEVICE_ID_INTEL_ICH10_4	0x3a30

#define PCI_DEVICE_ID_INTEL_HDA_ICH10_0	0x3a3e

#define PCI_DEVICE_ID_INTEL_ICH10_5	0x3a60

#define PCI_DEVICE_ID_INTEL_HDA_ICH10_1 0x3a6e

#define PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MIN	0x3b00

#define PCI_DEVICE_ID_INTEL_5_3400_SERIES_LPC_MAX	0x3b1f

#define PCI_DEVICE_ID_INTEL_HDA_5_3400_SERIES_0	0x3b56

#define PCI_DEVICE_ID_INTEL_HDA_5_3400_SERIES_1	0x3b57

#define PCI_DEVICE_ID_INTEL_IOAT_SNB0	0x3c20

#define PCI_DEVICE_ID_INTEL_IOAT_SNB1	0x3c21

#define PCI_DEVICE_ID_INTEL_IOAT_SNB2	0x3c22
@@ -2943,16 +2971,12 @@ 
#define PCI_DEVICE_ID_INTEL_IOAT_SNB7	0x3c27

#define PCI_DEVICE_ID_INTEL_IOAT_SNB8	0x3c2e

#define PCI_DEVICE_ID_INTEL_IOAT_SNB9	0x3c2f

#define PCI_DEVICE_ID_INTEL_UNC_HA	0x3c46

#define PCI_DEVICE_ID_INTEL_UNC_IMC0	0x3cb0

#define PCI_DEVICE_ID_INTEL_UNC_IMC1	0x3cb1

#define PCI_DEVICE_ID_INTEL_UNC_IMC2	0x3cb4

#define PCI_DEVICE_ID_INTEL_UNC_IMC3	0x3cb5

#define PCI_DEVICE_ID_INTEL_UNC_QPI0	0x3c41

#define PCI_DEVICE_ID_INTEL_UNC_QPI1	0x3c42

#define PCI_DEVICE_ID_INTEL_UNC_R2PCIE	0x3c43

#define PCI_DEVICE_ID_INTEL_UNC_R3QPI0	0x3c44

#define PCI_DEVICE_ID_INTEL_UNC_R3QPI1	0x3c45

#define PCI_DEVICE_ID_INTEL_UNC_HA	0x3c46

#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_RAS	0x3c71	/* 15.1 */

#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR0	0x3c72	/* 16.2 */

#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_ERR1	0x3c73	/* 16.3 */
@@ -2964,17 +2988,40 @@ 
#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD1	0x3cab	/* 15.3 */

#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD2	0x3cac	/* 15.4 */

#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_TAD3	0x3cad	/* 15.5 */

#define PCI_DEVICE_ID_INTEL_UNC_IMC0	0x3cb0

#define PCI_DEVICE_ID_INTEL_UNC_IMC1	0x3cb1

#define PCI_DEVICE_ID_INTEL_UNC_IMC2	0x3cb4

#define PCI_DEVICE_ID_INTEL_UNC_IMC3	0x3cb5

#define PCI_DEVICE_ID_INTEL_SBRIDGE_IMC_DDRIO	0x3cb8	/* 17.0 */

#define PCI_DEVICE_ID_INTEL_JAKETOWN_UBOX	0x3ce0

#define PCI_DEVICE_ID_INTEL_SBRIDGE_SAD0	0x3cf4	/* 12.6 */

#define PCI_DEVICE_ID_INTEL_SBRIDGE_BR		0x3cf5	/* 13.6 */

#define PCI_DEVICE_ID_INTEL_SBRIDGE_SAD1	0x3cf6	/* 12.7 */

#define PCI_DEVICE_ID_INTEL_HDA_ICL_H	0x3dc8

#define PCI_DEVICE_ID_INTEL_IOAT_SNB	0x402f

#define PCI_DEVICE_ID_INTEL_5400_ERR	0x4030

#define PCI_DEVICE_ID_INTEL_5400_FBD0	0x4035

#define PCI_DEVICE_ID_INTEL_5400_FBD1	0x4036

#define PCI_DEVICE_ID_INTEL_HDA_TGL_H	0x43c8

#define PCI_DEVICE_ID_INTEL_HDA_DG1	0x490d

#define PCI_DEVICE_ID_INTEL_HDA_EHL_0	0x4b55

#define PCI_DEVICE_ID_INTEL_HDA_EHL_3	0x4b58

#define PCI_DEVICE_ID_INTEL_HDA_JSL_N	0x4dc8

#define PCI_DEVICE_ID_INTEL_HDA_DG2_0	0x4f90

#define PCI_DEVICE_ID_INTEL_HDA_DG2_1	0x4f91

#define PCI_DEVICE_ID_INTEL_HDA_DG2_2	0x4f92

#define PCI_DEVICE_ID_INTEL_EP80579_0	0x5031

#define PCI_DEVICE_ID_INTEL_EP80579_1	0x5032

#define PCI_DEVICE_ID_INTEL_HDA_ADL_P	0x51c8

#define PCI_DEVICE_ID_INTEL_HDA_ADL_PS	0x51c9

#define PCI_DEVICE_ID_INTEL_HDA_RPL_P_0	0x51ca

#define PCI_DEVICE_ID_INTEL_HDA_RPL_P_1	0x51cb

#define PCI_DEVICE_ID_INTEL_HDA_ADL_M	0x51cc

#define PCI_DEVICE_ID_INTEL_HDA_ADL_PX	0x51cd

#define PCI_DEVICE_ID_INTEL_HDA_RPL_M	0x51ce

#define PCI_DEVICE_ID_INTEL_HDA_RPL_PX	0x51cf

#define PCI_DEVICE_ID_INTEL_HDA_ADL_N	0x54c8

#define PCI_DEVICE_ID_INTEL_HDA_APL	0x5a98

#define PCI_DEVICE_ID_INTEL_5100_16	0x65f0

#define PCI_DEVICE_ID_INTEL_5100_19	0x65f3

#define PCI_DEVICE_ID_INTEL_5100_21	0x65f5
@@ -3008,8 +3055,13 @@ 
#define PCI_DEVICE_ID_INTEL_82443GX_0	0x71a0

#define PCI_DEVICE_ID_INTEL_82443GX_2	0x71a2

#define PCI_DEVICE_ID_INTEL_82372FB_1	0x7601

#define PCI_DEVICE_ID_INTEL_HDA_RPL_S	0x7a50

#define PCI_DEVICE_ID_INTEL_HDA_ADL_S	0x7ad0

#define PCI_DEVICE_ID_INTEL_HDA_MTL	0x7e28

#define PCI_DEVICE_ID_INTEL_HDA_ARL_S	0x7f50

#define PCI_DEVICE_ID_INTEL_SCH_LPC	0x8119

#define PCI_DEVICE_ID_INTEL_SCH_IDE	0x811a

#define PCI_DEVICE_ID_INTEL_HDA_POULSBO	0x811b

#define PCI_DEVICE_ID_INTEL_E6XX_CU	0x8183

#define PCI_DEVICE_ID_INTEL_ITC_LPC	0x8186

#define PCI_DEVICE_ID_INTEL_82454GX	0x84c4
@@ -3018,9 +3070,31 @@ 
#define PCI_DEVICE_ID_INTEL_82454NX     0x84cb

#define PCI_DEVICE_ID_INTEL_84460GX	0x84ea

#define PCI_DEVICE_ID_INTEL_IXP4XX	0x8500

#define PCI_DEVICE_ID_INTEL_HDA_LPT	0x8c20

#define PCI_DEVICE_ID_INTEL_HDA_9_SERIES	0x8ca0

#define PCI_DEVICE_ID_INTEL_HDA_WBG_0	0x8d20

#define PCI_DEVICE_ID_INTEL_HDA_WBG_1	0x8d21

#define PCI_DEVICE_ID_INTEL_IXP2800	0x9004

#define PCI_DEVICE_ID_INTEL_HDA_LKF	0x98c8

#define PCI_DEVICE_ID_INTEL_VMD_9A0B	0x9a0b

#define PCI_DEVICE_ID_INTEL_HDA_LPT_LP_0	0x9c20

#define PCI_DEVICE_ID_INTEL_HDA_LPT_LP_1	0x9c21

#define PCI_DEVICE_ID_INTEL_HDA_WPT_LP	0x9ca0

#define PCI_DEVICE_ID_INTEL_HDA_SKL_LP	0x9d70

#define PCI_DEVICE_ID_INTEL_HDA_KBL_LP	0x9d71

#define PCI_DEVICE_ID_INTEL_HDA_CNL_LP	0x9dc8

#define PCI_DEVICE_ID_INTEL_HDA_TGL_LP	0xa0c8

#define PCI_DEVICE_ID_INTEL_HDA_SKL	0xa170

#define PCI_DEVICE_ID_INTEL_HDA_KBL	0xa171

#define PCI_DEVICE_ID_INTEL_HDA_LBG_0	0xa1f0

#define PCI_DEVICE_ID_INTEL_HDA_LBG_1	0xa270

#define PCI_DEVICE_ID_INTEL_HDA_KBL_H	0xa2f0

#define PCI_DEVICE_ID_INTEL_HDA_CNL_H	0xa348

#define PCI_DEVICE_ID_INTEL_HDA_CML_S	0xa3f0

#define PCI_DEVICE_ID_INTEL_HDA_LNL_P	0xa828

#define PCI_DEVICE_ID_INTEL_S21152BB	0xb152

#define PCI_DEVICE_ID_INTEL_HDA_CML_R	0xf0c8

#define PCI_DEVICE_ID_INTEL_HDA_RKL_S	0xf1c8



#define PCI_VENDOR_ID_WANGXUN		0x8088

include/sound/hda-mlink.h

+4 −0
Original line number Diff line number Diff line
@@ -42,6 +42,7 @@ int hdac_bus_eml_power_down_unlocked(struct hdac_bus *bus, bool alt, int elid, i 
int hdac_bus_eml_sdw_power_up_unlocked(struct hdac_bus *bus, int sublink);

int hdac_bus_eml_sdw_power_down_unlocked(struct hdac_bus *bus, int sublink);



int hdac_bus_eml_sdw_get_lsdiid_unlocked(struct hdac_bus *bus, int sublink, u16 *lsdiid);

int hdac_bus_eml_sdw_set_lsdiid(struct hdac_bus *bus, int sublink, int dev_num);



int hdac_bus_eml_sdw_map_stream_ch(struct hdac_bus *bus, int sublink, int y,
@@ -145,6 +146,9 @@ hdac_bus_eml_sdw_power_up_unlocked(struct hdac_bus *bus, int sublink) { return 0 
static inline int

hdac_bus_eml_sdw_power_down_unlocked(struct hdac_bus *bus, int sublink) { return 0; }



static inline int

hdac_bus_eml_sdw_get_lsdiid_unlocked(struct hdac_bus *bus, int sublink, u16 *lsdiid) { return 0; }



static inline int

hdac_bus_eml_sdw_set_lsdiid(struct hdac_bus *bus, int sublink, int dev_num) { return 0; }

include/sound/hda_codec.h

+0 −3
Original line number Diff line number Diff line
@@ -18,9 +18,6 @@ 
#include <sound/hda_verbs.h>

#include <sound/hda_regmap.h>



#define IS_BXT(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0x5a98)

#define IS_CFL(pci) ((pci)->vendor == 0x8086 && (pci)->device == 0xa348)



/*

 * Structures

 */

include/sound/hdaudio.h

+26 −0
Original line number Diff line number Diff line
@@ -11,6 +11,7 @@ 
#include <linux/io.h>

#include <linux/io-64-nonatomic-lo-hi.h>

#include <linux/iopoll.h>

#include <linux/pci.h>

#include <linux/pm_runtime.h>

#include <linux/timecounter.h>

#include <sound/core.h>
@@ -704,4 +705,29 @@ static inline unsigned int snd_array_index(struct snd_array *array, void *ptr) 
	for ((idx) = 0, (ptr) = (array)->list; (idx) < (array)->used; \

	     (ptr) = snd_array_elem(array, ++(idx)))



/*

 * Device matching

 */



#define HDA_CONTROLLER_IS_HSW(pci) (pci_match_id((struct pci_device_id []){ \

			{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_HSW_0) }, \

			{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_HSW_2) }, \

			{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_HSW_3) }, \

			{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_BDW) }, \

			{ } \

		}, pci))



#define HDA_CONTROLLER_IS_APL(pci) (pci_match_id((struct pci_device_id []){ \

			{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_APL) }, \

			{ } \

		}, pci))



#define HDA_CONTROLLER_IN_GPU(pci) (pci_match_id((struct pci_device_id []){ \

			{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_DG1) }, \

			{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_DG2_0) }, \

			{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_DG2_1) }, \

			{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HDA_DG2_2) }, \

			{ } \

		}, pci) || HDA_CONTROLLER_IS_HSW(pci))



#endif /* __SOUND_HDAUDIO_H */

sound/hda/hdac_i915.c

+11 −10
Original line number Diff line number Diff line
@@ -11,11 +11,6 @@ 
#include <sound/hda_i915.h>

#include <sound/hda_register.h>



#define IS_HSW_CONTROLLER(pci) (((pci)->device == 0x0a0c) || \

				((pci)->device == 0x0c0c) || \

				((pci)->device == 0x0d0c) || \

				((pci)->device == 0x160c))



/**

 * snd_hdac_i915_set_bclk - Reprogram BCLK for HSW/BDW

 * @bus: HDA core bus
@@ -39,7 +34,7 @@ void snd_hdac_i915_set_bclk(struct hdac_bus *bus) 


	if (!acomp || !acomp->ops || !acomp->ops->get_cdclk_freq)

		return; /* only for i915 binding */

	if (!IS_HSW_CONTROLLER(pci))

	if (!HDA_CONTROLLER_IS_HSW(pci))

		return; /* only HSW/BDW */



	cdclk_freq = acomp->ops->get_cdclk_freq(acomp->dev);
@@ -80,14 +75,20 @@ static bool connectivity_check(struct pci_dev *i915, struct pci_dev *hdac) 
	if (bus_a == bus_b)

		return true;



	/*

	 * on i915 discrete GPUs with embedded HDA audio, the two

	 * devices are connected via 2nd level PCI bridge

	 */

	bus_a = bus_a->parent;

	bus_b = bus_b->parent;



	/* connected via parent bus (may be NULL!) */

	if (bus_a == bus_b)

		return true;



	if (!bus_a || !bus_b)

		return false;



	/*

	 * on i915 discrete GPUs with embedded HDA audio, the two

	 * devices are connected via 2nd level PCI bridge

	 */

	bus_a = bus_a->parent;

	bus_b = bus_b->parent;

	if (bus_a && bus_a == bus_b)