Commit 4460e457 authored by Jakub Kicinski's avatar Jakub Kicinski
Browse files

Merge branch '100GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/tnguy/net-queue 

Tony Nguyen says:

====================
Intel Wired LAN Driver Updates 2025-01-07 (ice, igc)

For ice:

Arkadiusz corrects mask value being used to determine DPLL phase range.

Przemyslaw corrects frequency value for E823 devices.

For igc:

En-Wei Wu adds a check and, early, return for failed register read.

* '100GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/tnguy/net-queue:
  igc: return early when failing to read EECD register
  ice: fix incorrect PHY settings for 100 GB/s
  ice: fix max values for dpll pin phase adjust
====================

Link: https://patch.msgid.link/20250107190150.1758577-1-anthony.l.nguyen@intel.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parents 6730ee8f bd2776e3

drivers/net/ethernet/intel/ice/ice_adminq_cmd.h

+2 −0
Original line number Diff line number Diff line
@@ -2264,6 +2264,8 @@ struct ice_aqc_get_pkg_info_resp { 
	struct ice_aqc_get_pkg_info pkg_info[];

};



#define ICE_AQC_GET_CGU_MAX_PHASE_ADJ	GENMASK(30, 0)



/* Get CGU abilities command response data structure (indirect 0x0C61) */

struct ice_aqc_get_cgu_abilities {

	u8 num_inputs;

drivers/net/ethernet/intel/ice/ice_dpll.c

+23 −12
Original line number Diff line number Diff line
@@ -2064,6 +2064,18 @@ static int ice_dpll_init_worker(struct ice_pf *pf) 
	return 0;

}



/**

 * ice_dpll_phase_range_set - initialize phase adjust range helper

 * @range: pointer to phase adjust range struct to be initialized

 * @phase_adj: a value to be used as min(-)/max(+) boundary

 */

static void ice_dpll_phase_range_set(struct dpll_pin_phase_adjust_range *range,

				     u32 phase_adj)

{

	range->min = -phase_adj;

	range->max = phase_adj;

}



/**

 * ice_dpll_init_info_pins_generic - initializes generic pins info

 * @pf: board private structure
@@ -2105,8 +2117,8 @@ static int ice_dpll_init_info_pins_generic(struct ice_pf *pf, bool input) 
	for (i = 0; i < pin_num; i++) {

		pins[i].idx = i;

		pins[i].prop.board_label = labels[i];

		pins[i].prop.phase_range.min = phase_adj_max;

		pins[i].prop.phase_range.max = -phase_adj_max;

		ice_dpll_phase_range_set(&pins[i].prop.phase_range,

					 phase_adj_max);

		pins[i].prop.capabilities = cap;

		pins[i].pf = pf;

		ret = ice_dpll_pin_state_update(pf, &pins[i], pin_type, NULL);
@@ -2152,6 +2164,7 @@ ice_dpll_init_info_direct_pins(struct ice_pf *pf, 
	struct ice_hw *hw = &pf->hw;

	struct ice_dpll_pin *pins;

	unsigned long caps;

	u32 phase_adj_max;

	u8 freq_supp_num;

	bool input;
@@ -2159,11 +2172,13 @@ ice_dpll_init_info_direct_pins(struct ice_pf *pf, 
	case ICE_DPLL_PIN_TYPE_INPUT:

		pins = pf->dplls.inputs;

		num_pins = pf->dplls.num_inputs;

		phase_adj_max = pf->dplls.input_phase_adj_max;

		input = true;

		break;

	case ICE_DPLL_PIN_TYPE_OUTPUT:

		pins = pf->dplls.outputs;

		num_pins = pf->dplls.num_outputs;

		phase_adj_max = pf->dplls.output_phase_adj_max;

		input = false;

		break;

	default:
@@ -2188,19 +2203,13 @@ ice_dpll_init_info_direct_pins(struct ice_pf *pf, 
				return ret;

			caps |= (DPLL_PIN_CAPABILITIES_PRIORITY_CAN_CHANGE |

				 DPLL_PIN_CAPABILITIES_STATE_CAN_CHANGE);

			pins[i].prop.phase_range.min =

				pf->dplls.input_phase_adj_max;

			pins[i].prop.phase_range.max =

				-pf->dplls.input_phase_adj_max;

		} else {

			pins[i].prop.phase_range.min =

				pf->dplls.output_phase_adj_max;

			pins[i].prop.phase_range.max =

				-pf->dplls.output_phase_adj_max;

			ret = ice_cgu_get_output_pin_state_caps(hw, i, &caps);

			if (ret)

				return ret;

		}

		ice_dpll_phase_range_set(&pins[i].prop.phase_range,

					 phase_adj_max);

		pins[i].prop.capabilities = caps;

		ret = ice_dpll_pin_state_update(pf, &pins[i], pin_type, NULL);

		if (ret)
@@ -2308,8 +2317,10 @@ static int ice_dpll_init_info(struct ice_pf *pf, bool cgu) 
	dp->dpll_idx = abilities.pps_dpll_idx;

	d->num_inputs = abilities.num_inputs;

	d->num_outputs = abilities.num_outputs;

	d->input_phase_adj_max = le32_to_cpu(abilities.max_in_phase_adj);

	d->output_phase_adj_max = le32_to_cpu(abilities.max_out_phase_adj);

	d->input_phase_adj_max = le32_to_cpu(abilities.max_in_phase_adj) &

		ICE_AQC_GET_CGU_MAX_PHASE_ADJ;

	d->output_phase_adj_max = le32_to_cpu(abilities.max_out_phase_adj) &

		ICE_AQC_GET_CGU_MAX_PHASE_ADJ;



	alloc_size = sizeof(*d->inputs) * d->num_inputs;

	d->inputs = kzalloc(alloc_size, GFP_KERNEL);

drivers/net/ethernet/intel/ice/ice_ptp_consts.h

+2 −2
Original line number Diff line number Diff line
@@ -761,9 +761,9 @@ const struct ice_vernier_info_e82x e822_vernier[NUM_ICE_PTP_LNK_SPD] = { 
		/* rx_desk_rsgb_par */

		644531250, /* 644.53125 MHz Reed Solomon gearbox */

		/* tx_desk_rsgb_pcs */

		644531250, /* 644.53125 MHz Reed Solomon gearbox */

		390625000, /* 390.625 MHz Reed Solomon gearbox */

		/* rx_desk_rsgb_pcs */

		644531250, /* 644.53125 MHz Reed Solomon gearbox */

		390625000, /* 390.625 MHz Reed Solomon gearbox */

		/* tx_fixed_delay */

		1620,

		/* pmd_adj_divisor */

drivers/net/ethernet/intel/igc/igc_base.c

+6 −0
Original line number Diff line number Diff line
@@ -68,6 +68,10 @@ static s32 igc_init_nvm_params_base(struct igc_hw *hw) 
	u32 eecd = rd32(IGC_EECD);

	u16 size;



	/* failed to read reg and got all F's */

	if (!(~eecd))

		return -ENXIO;



	size = FIELD_GET(IGC_EECD_SIZE_EX_MASK, eecd);



	/* Added to a constant, "size" becomes the left-shift value
@@ -221,6 +225,8 @@ static s32 igc_get_invariants_base(struct igc_hw *hw) 


	/* NVM initialization */

	ret_val = igc_init_nvm_params_base(hw);

	if (ret_val)

		goto out;

	switch (hw->mac.type) {

	case igc_i225:

		ret_val = igc_init_nvm_params_i225(hw);