Commit 44892ffa authored by Dave Airlie's avatar Dave Airlie Committed by Jani Nikula
Browse files

drm/i915: add wrappers around cdclk vtable funcs. 



This adds wrappers around all the vtable callers so they are in
one place.

Suggested by Jani.

Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarDave Airlie <airlied@redhat.com>
Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/c3dd7aaad039e76acde9dda7211468907aa657c0.1632869550.git.jani.nikula@intel.com
parent 02a1a635

drivers/gpu/drm/i915/display/intel_cdclk.c

+39 −8
Original line number Diff line number Diff line
@@ -59,6 +59,37 @@ 
 * dividers can be programmed correctly.

 */



void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv,

			   struct intel_cdclk_config *cdclk_config)

{

	dev_priv->display.get_cdclk(dev_priv, cdclk_config);

}



int intel_cdclk_bw_calc_min_cdclk(struct intel_atomic_state *state)

{

	struct drm_i915_private *dev_priv = to_i915(state->base.dev);

	return dev_priv->display.bw_calc_min_cdclk(state);

}



static void intel_cdclk_set_cdclk(struct drm_i915_private *dev_priv,

				  const struct intel_cdclk_config *cdclk_config,

				  enum pipe pipe)

{

	dev_priv->display.set_cdclk(dev_priv, cdclk_config, pipe);

}



static int intel_cdclk_modeset_calc_cdclk(struct drm_i915_private *dev_priv,

					  struct intel_cdclk_state *cdclk_config)

{

	return dev_priv->display.modeset_calc_cdclk(cdclk_config);

}



static u8 intel_cdclk_calc_voltage_level(struct drm_i915_private *dev_priv,

					 int cdclk)

{

	return dev_priv->display.calc_voltage_level(cdclk);

}



static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv,

				   struct intel_cdclk_config *cdclk_config)

{
@@ -1466,7 +1497,7 @@ static void bxt_get_cdclk(struct drm_i915_private *dev_priv, 
	 * at least what the CDCLK frequency requires.

	 */

	cdclk_config->voltage_level =

		dev_priv->display.calc_voltage_level(cdclk_config->cdclk);

		intel_cdclk_calc_voltage_level(dev_priv, cdclk_config->cdclk);

}



static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
@@ -1777,7 +1808,7 @@ static void bxt_cdclk_init_hw(struct drm_i915_private *dev_priv) 
	cdclk_config.cdclk = bxt_calc_cdclk(dev_priv, 0);

	cdclk_config.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_config.cdclk);

	cdclk_config.voltage_level =

		dev_priv->display.calc_voltage_level(cdclk_config.cdclk);

		intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk);



	bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);

}
@@ -1789,7 +1820,7 @@ static void bxt_cdclk_uninit_hw(struct drm_i915_private *dev_priv) 
	cdclk_config.cdclk = cdclk_config.bypass;

	cdclk_config.vco = 0;

	cdclk_config.voltage_level =

		dev_priv->display.calc_voltage_level(cdclk_config.cdclk);

		intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk);



	bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);

}
@@ -1956,7 +1987,7 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv, 
				     &dev_priv->gmbus_mutex);

	}



	dev_priv->display.set_cdclk(dev_priv, cdclk_config, pipe);

	intel_cdclk_set_cdclk(dev_priv, cdclk_config, pipe);



	for_each_intel_dp(&dev_priv->drm, encoder) {

		struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
@@ -2422,7 +2453,7 @@ static int bxt_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state) 
	cdclk_state->logical.cdclk = cdclk;

	cdclk_state->logical.voltage_level =

		max_t(int, min_voltage_level,

		      dev_priv->display.calc_voltage_level(cdclk));

		      intel_cdclk_calc_voltage_level(dev_priv, cdclk));



	if (!cdclk_state->active_pipes) {

		cdclk = bxt_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk);
@@ -2431,7 +2462,7 @@ static int bxt_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state) 
		cdclk_state->actual.vco = vco;

		cdclk_state->actual.cdclk = cdclk;

		cdclk_state->actual.voltage_level =

			dev_priv->display.calc_voltage_level(cdclk);

			intel_cdclk_calc_voltage_level(dev_priv, cdclk);

	} else {

		cdclk_state->actual = cdclk_state->logical;

	}
@@ -2523,7 +2554,7 @@ int intel_modeset_calc_cdclk(struct intel_atomic_state *state) 
	new_cdclk_state->active_pipes =

		intel_calc_active_pipes(state, old_cdclk_state->active_pipes);



	ret = dev_priv->display.modeset_calc_cdclk(new_cdclk_state);

	ret = intel_cdclk_modeset_calc_cdclk(dev_priv, new_cdclk_state);

	if (ret)

		return ret;
@@ -2703,7 +2734,7 @@ void intel_update_max_cdclk(struct drm_i915_private *dev_priv) 
 */

void intel_update_cdclk(struct drm_i915_private *dev_priv)

{

	dev_priv->display.get_cdclk(dev_priv, &dev_priv->cdclk.hw);

	intel_cdclk_get_cdclk(dev_priv, &dev_priv->cdclk.hw);



	/*

	 * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):

drivers/gpu/drm/i915/display/intel_cdclk.h

+3 −1
Original line number Diff line number Diff line
@@ -68,7 +68,9 @@ void intel_set_cdclk_post_plane_update(struct intel_atomic_state *state); 
void intel_dump_cdclk_config(const struct intel_cdclk_config *cdclk_config,

			     const char *context);

int intel_modeset_calc_cdclk(struct intel_atomic_state *state);



void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv,

			   struct intel_cdclk_config *cdclk_config);

int intel_cdclk_bw_calc_min_cdclk(struct intel_atomic_state *state);

struct intel_cdclk_state *

intel_atomic_get_cdclk_state(struct intel_atomic_state *state);

drivers/gpu/drm/i915/display/intel_display.c

+1 −1
Original line number Diff line number Diff line
@@ -9159,7 +9159,7 @@ static int intel_atomic_check_cdclk(struct intel_atomic_state *state, 
	    old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk)

		*need_cdclk_calc = true;



	ret = dev_priv->display.bw_calc_min_cdclk(state);

	ret = intel_cdclk_bw_calc_min_cdclk(state);

	if (ret)

		return ret;

drivers/gpu/drm/i915/display/intel_display_power.c

+1 −1
Original line number Diff line number Diff line
@@ -1195,7 +1195,7 @@ static void gen9_disable_dc_states(struct drm_i915_private *dev_priv) 
	if (!HAS_DISPLAY(dev_priv))

		return;



	dev_priv->display.get_cdclk(dev_priv, &cdclk_config);

	intel_cdclk_get_cdclk(dev_priv, &cdclk_config);

	/* Can't read out voltage_level so can't use intel_cdclk_changed() */

	drm_WARN_ON(&dev_priv->drm,

		    intel_cdclk_needs_modeset(&dev_priv->cdclk.hw,