Commit 455061eb authored by André Draszik's avatar André Draszik Committed by Krzysztof Kozlowski
Browse files

dt-bindings: clock: google,gs101-clock: add PERIC1 clock management unit



Add dt-schema documentation and clock IDs for the Connectivity
Peripheral 1 (PERIC1) clock management unit.

Signed-off-by: default avatarAndré Draszik <andre.draszik@linaro.org>
Reviewed-by: default avatarSam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: default avatarPeter Griffin <peter.griffin@linaro.org>
Reviewed-by: default avatarTudor Ambarus <tudor.ambarus@linaro.org>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20240201161258.1013664-3-andre.draszik@linaro.org


Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
parent bc8cc7fb
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+6 −3
Original line number Diff line number Diff line
@@ -31,6 +31,7 @@ properties:
      - google,gs101-cmu-apm
      - google,gs101-cmu-misc
      - google,gs101-cmu-peric0
      - google,gs101-cmu-peric1

  clocks:
    minItems: 1
@@ -93,15 +94,17 @@ allOf:
      properties:
        compatible:
          contains:
            const: google,gs101-cmu-peric0
            enum:
              - google,gs101-cmu-peric0
              - google,gs101-cmu-peric1

    then:
      properties:
        clocks:
          items:
            - description: External reference clock (24.576 MHz)
            - description: Connectivity Peripheral 0 bus clock (from CMU_TOP)
            - description: Connectivity Peripheral 0 IP clock (from CMU_TOP)
            - description: Connectivity Peripheral 0/1 bus clock (from CMU_TOP)
            - description: Connectivity Peripheral 0/1 IP clock (from CMU_TOP)

        clock-names:
          items:
+48 −0
Original line number Diff line number Diff line
@@ -470,4 +470,52 @@
#define CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK		78
#define CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK		79

/* CMU_PERIC1 */
#define CLK_MOUT_PERIC1_BUS_USER			1
#define CLK_MOUT_PERIC1_I3C_USER			2
#define CLK_MOUT_PERIC1_USI0_USI_USER			3
#define CLK_MOUT_PERIC1_USI10_USI_USER			4
#define CLK_MOUT_PERIC1_USI11_USI_USER			5
#define CLK_MOUT_PERIC1_USI12_USI_USER			6
#define CLK_MOUT_PERIC1_USI13_USI_USER			7
#define CLK_MOUT_PERIC1_USI9_USI_USER			8
#define CLK_DOUT_PERIC1_I3C				9
#define CLK_DOUT_PERIC1_USI0_USI			10
#define CLK_DOUT_PERIC1_USI10_USI			11
#define CLK_DOUT_PERIC1_USI11_USI			12
#define CLK_DOUT_PERIC1_USI12_USI			13
#define CLK_DOUT_PERIC1_USI13_USI			14
#define CLK_DOUT_PERIC1_USI9_USI			15
#define CLK_GOUT_PERIC1_IP				16
#define CLK_GOUT_PERIC1_PCLK				17
#define CLK_GOUT_PERIC1_CLK_PERIC1_I3C_CLK		18
#define CLK_GOUT_PERIC1_CLK_PERIC1_OSCCLK_CLK		19
#define CLK_GOUT_PERIC1_D_TZPC_PERIC1_PCLK		20
#define CLK_GOUT_PERIC1_GPC_PERIC1_PCLK			21
#define CLK_GOUT_PERIC1_GPIO_PERIC1_PCLK		22
#define CLK_GOUT_PERIC1_LHM_AXI_P_PERIC1_I_CLK		23
#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1		24
#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2		25
#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3		26
#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4		27
#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5		28
#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6		29
#define CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_8		30
#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1		31
#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_15		32
#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2		33
#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3		34
#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4		35
#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5		36
#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6		37
#define CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_8		38
#define CLK_GOUT_PERIC1_CLK_PERIC1_BUSP_CLK		39
#define CLK_GOUT_PERIC1_CLK_PERIC1_USI0_USI_CLK		40
#define CLK_GOUT_PERIC1_CLK_PERIC1_USI10_USI_CLK	41
#define CLK_GOUT_PERIC1_CLK_PERIC1_USI11_USI_CLK	42
#define CLK_GOUT_PERIC1_CLK_PERIC1_USI12_USI_CLK	43
#define CLK_GOUT_PERIC1_CLK_PERIC1_USI13_USI_CLK	44
#define CLK_GOUT_PERIC1_CLK_PERIC1_USI9_USI_CLK		45
#define CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK		46

#endif /* _DT_BINDINGS_CLOCK_GOOGLE_GS101_H */