Commit 4551d602 authored by Tejas Upadhyay's avatar Tejas Upadhyay Committed by Lucas De Marchi
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drm/xe: Define STATELESS_COMPRESSION_CTRL as mcr register 



Register STATELESS_COMPRESSION_CTRL should be considered
mcr register which should write to all slices as per
documentation.

Bspec: 71185
Fixes: ecabb5e6 ("drm/xe/xe2: Add performance turning changes")
Signed-off-by: default avatarTejas Upadhyay <tejas.upadhyay@intel.com>
Reviewed-by: default avatarShekhar Chauhan <shekhar.chauhan@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240814095614.909774-4-tejas.upadhyay@intel.com


Signed-off-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
parent f0ffa657

drivers/gpu/drm/xe/regs/xe_gt_regs.h

+1 −1
Original line number Diff line number Diff line
@@ -80,7 +80,7 @@ 
#define   LE_CACHEABILITY_MASK			REG_GENMASK(1, 0)

#define   LE_CACHEABILITY(value)		REG_FIELD_PREP(LE_CACHEABILITY_MASK, value)



#define STATELESS_COMPRESSION_CTRL		XE_REG(0x4148)

#define STATELESS_COMPRESSION_CTRL		XE_REG_MCR(0x4148)

#define   UNIFIED_COMPRESSION_FORMAT		REG_GENMASK(3, 0)



#define XE2_GAMREQSTRM_CTRL			XE_REG_MCR(0x4194)