Unverified Commit 45682a4f authored by AngeloGioacchino Del Regno's avatar AngeloGioacchino Del Regno
Browse files

arm64: dts: mediatek: mt8188: Add Global Command Engine mailboxes 

In preparation for adding multimedia nodes and power domains, add
support for the two Global Command Engine (GCE) mailboxes found in
this SoC.

Link: https://lore.kernel.org/r/20240527093908.97574-3-angelogioacchino.delregno@collabora.com


Signed-off-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
parent b220332f

arch/arm64/boot/dts/mediatek/mt8188.dtsi

+17 −0
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ 
#include <dt-bindings/clock/mediatek,mt8188-clk.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/interrupt-controller/irq.h>

#include <dt-bindings/mailbox/mediatek,mt8188-gce.h>

#include <dt-bindings/phy/phy.h>

#include <dt-bindings/pinctrl/mediatek,mt8188-pinfunc.h>

#include <dt-bindings/power/mediatek,mt8188-power.h>
@@ -413,6 +414,22 @@ pwrap: pwrap@10024000 { 
			clock-names = "spi", "wrap";

		};



		gce0: mailbox@10320000 {

			compatible = "mediatek,mt8188-gce";

			reg = <0 0x10320000 0 0x4000>;

			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>;

			#mbox-cells = <2>;

			clocks = <&infracfg_ao CLK_INFRA_AO_GCE>;

		};



		gce1: mailbox@10330000 {

			compatible = "mediatek,mt8188-gce";

			reg = <0 0x10330000 0 0x4000>;

			interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH 0>;

			#mbox-cells = <2>;

			clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>;

		};



		scp: scp@10500000 {

			compatible = "mediatek,mt8188-scp";

			reg = <0 0x10500000 0 0x100000>,