Commit 466a6c38 authored by Michal Wajdeczko's avatar Michal Wajdeczko
Browse files

drm/xe: Kill regs/xe_sriov_regs.h 



There is no real benefit to maintain a separate file. The register
definitions related to SR-IOV can be placed in existing headers.

Signed-off-by: default avatarMichal Wajdeczko <michal.wajdeczko@intel.com>
Reviewed-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Reviewed-by: default avatarHimal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240702183704.1022-3-michal.wajdeczko@intel.com
parent 9dae9751

drivers/gpu/drm/xe/regs/xe_gt_regs.h

+6 −0
Original line number Diff line number Diff line
@@ -88,6 +88,8 @@ 
#define VE1_AUX_INV				XE_REG(0x42b8)

#define   AUX_INV				REG_BIT(0)



#define XE2_LMEM_CFG				XE_REG(0x48b0)



#define XEHP_TILE_ADDR_RANGE(_idx)		XE_REG_MCR(0x4900 + (_idx) * 4)

#define XEHP_FLAT_CCS_BASE_ADDR			XE_REG_MCR(0x4910)

#define XEHP_FLAT_CCS_PTR			REG_GENMASK(31, 8)
@@ -395,6 +397,10 @@ 
#define   INVALIDATION_BROADCAST_MODE_DIS	REG_BIT(12)

#define   GLOBAL_INVALIDATION_MODE		REG_BIT(2)



#define LMEM_CFG				XE_REG(0xcf58)

#define   LMEM_EN				REG_BIT(31)

#define   LMTT_DIR_PTR				REG_GENMASK(30, 0) /* in multiples of 64KB */



#define HALF_SLICE_CHICKEN5			XE_REG_MCR(0xe188, XE_REG_OPTION_MASKED)

#define   DISABLE_SAMPLE_G_PERFORMANCE		REG_BIT(0)

drivers/gpu/drm/xe/regs/xe_regs.h

+6 −0
Original line number Diff line number Diff line
@@ -30,6 +30,9 @@ 
#define GU_DEBUG				XE_REG(0x101018)

#define   DRIVERFLR_STATUS			REG_BIT(31)



#define VIRTUAL_CTRL_REG			XE_REG(0x10108c)

#define   GUEST_GTT_UPDATE_EN			REG_BIT(8)



#define XEHP_MTCFG_ADDR				XE_REG(0x101800)

#define   TILE_COUNT				REG_GENMASK(15, 8)
@@ -66,6 +69,9 @@ 
#define   DISPLAY_IRQ				REG_BIT(16)

#define   GT_DW_IRQ(x)				REG_BIT(x)



#define VF_CAP_REG				XE_REG(0x1901f8, XE_REG_OPTION_VF)

#define   VF_CAP				REG_BIT(0)



#define PVC_RP_STATE_CAP			XE_REG(0x281014)



#endif

drivers/gpu/drm/xe/regs/xe_sriov_regs.h

deleted100644 → 0
+0 −23
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: MIT */

/*

 * Copyright © 2023 Intel Corporation

 */



#ifndef _REGS_XE_SRIOV_REGS_H_

#define _REGS_XE_SRIOV_REGS_H_



#include "regs/xe_reg_defs.h"



#define XE2_LMEM_CFG			XE_REG(0x48b0)



#define LMEM_CFG			XE_REG(0xcf58)

#define   LMEM_EN			REG_BIT(31)

#define   LMTT_DIR_PTR			REG_GENMASK(30, 0) /* in multiples of 64KB */



#define VIRTUAL_CTRL_REG		XE_REG(0x10108c)

#define   GUEST_GTT_UPDATE_EN		REG_BIT(8)



#define VF_CAP_REG			XE_REG(0x1901f8, XE_REG_OPTION_VF)

#define   VF_CAP			REG_BIT(0)



#endif

drivers/gpu/drm/xe/xe_gt_sriov_pf.c

+1 −1
Original line number Diff line number Diff line
@@ -5,7 +5,7 @@ 


#include <drm/drm_managed.h>



#include "regs/xe_sriov_regs.h"

#include "regs/xe_regs.h"



#include "xe_gt_sriov_pf.h"

#include "xe_gt_sriov_pf_config.h"

drivers/gpu/drm/xe/xe_lmtt.c

+1 −1
Original line number Diff line number Diff line
@@ -7,7 +7,7 @@ 


#include <drm/drm_managed.h>



#include "regs/xe_sriov_regs.h"

#include "regs/xe_gt_regs.h"



#include "xe_assert.h"

#include "xe_bo.h"