Commit 469df8c2 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov
Browse files

drm/msm/dpu: correct DP MST interface configuration



Due to historical reasons we ended up with dummy values being specified
for MST-related interfaces some of them had INTF_NONE, others had
non-existing DP controller indices. Those workarounds are no longer
necessary. Fix types and indices for all DP-MST related INTF instances.

The only exception is INTF_3 on SC8180X, which has unique design. It can
be used either with INTF_0 / DP0 or with INTF_4 / DP1. This interface is
left with the dummy value until somebody implements necessary bits for
that platform.

Co-developed-by: default avatarAbhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: default avatarAbhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: default avatarYongxing Mou <yongxing.mou@oss.qualcomm.com>
Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Patchwork: https://patchwork.freedesktop.org/patch/713988/
Link: https://lore.kernel.org/r/20260325-fix-dp-mst-interfaces-v1-1-186d1de3fa1b@oss.qualcomm.com
parent e224e3a1
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+1 −1
Original line number Diff line number Diff line
@@ -377,7 +377,7 @@ static const struct dpu_intf_cfg sm8650_intf[] = {
		.name = "intf_3", .id = INTF_3,
		.base = 0x37000, .len = 0x280,
		.type = INTF_DP,
		.controller_id = MSM_DP_CONTROLLER_1,
		.controller_id = MSM_DP_CONTROLLER_0,	/* pair with intf_0 for DP MST */
		.prog_fetch_lines_worst_case = 24,
		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
+1 −1
Original line number Diff line number Diff line
@@ -419,7 +419,7 @@ static const struct dpu_intf_cfg sm8750_intf[] = {
		.name = "intf_3", .id = INTF_3,
		.base = 0x37000, .len = 0x4bc,
		.type = INTF_DP,
		.controller_id = MSM_DP_CONTROLLER_1,
		.controller_id = MSM_DP_CONTROLLER_0,	/* pair with intf_0 for DP MST */
		.prog_fetch_lines_worst_case = 24,
		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
+3 −3
Original line number Diff line number Diff line
@@ -425,7 +425,7 @@ static const struct dpu_intf_cfg glymur_intf[] = {
	}, {
		.name = "intf_3", .id = INTF_3,
		.base = 0x37000, .len = 0x400,
		.type = INTF_NONE,
		.type = INTF_DP,
		.controller_id = MSM_DP_CONTROLLER_0,	/* pair with intf_0 for DP MST */
		.prog_fetch_lines_worst_case = 24,
		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
@@ -457,7 +457,7 @@ static const struct dpu_intf_cfg glymur_intf[] = {
	}, {
		.name = "intf_7", .id = INTF_7,
		.base = 0x3b000, .len = 0x400,
		.type = INTF_NONE,
		.type = INTF_DP,
		.controller_id = MSM_DP_CONTROLLER_2,	/* pair with intf_6 for DP MST */
		.prog_fetch_lines_worst_case = 24,
		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 18),
@@ -465,7 +465,7 @@ static const struct dpu_intf_cfg glymur_intf[] = {
	}, {
		.name = "intf_8", .id = INTF_8,
		.base = 0x3c000, .len = 0x400,
		.type = INTF_NONE,
		.type = INTF_DP,
		.controller_id = MSM_DP_CONTROLLER_1,	/* pair with intf_4 for DP MST */
		.prog_fetch_lines_worst_case = 24,
		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),
+1 −1
Original line number Diff line number Diff line
@@ -417,7 +417,7 @@ static const struct dpu_intf_cfg kaanapali_intf[] = {
		.name = "intf_3", .id = INTF_3,
		.base = 0x190000, .len = 0x4bc,
		.type = INTF_DP,
		.controller_id = MSM_DP_CONTROLLER_1,
		.controller_id = MSM_DP_CONTROLLER_0,	/* pair with intf_0 for DP MST */
		.prog_fetch_lines_worst_case = 24,
		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
+1 −1
Original line number Diff line number Diff line
@@ -258,7 +258,7 @@ static const struct dpu_intf_cfg sdm845_intf[] = {
		.name = "intf_3", .id = INTF_3,
		.base = 0x6b800, .len = 0x280,
		.type = INTF_DP,
		.controller_id = MSM_DP_CONTROLLER_1,
		.controller_id = MSM_DP_CONTROLLER_0,	/* pair with intf_0 for DP MST */
		.prog_fetch_lines_worst_case = 24,
		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
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