Commit 46c56b73 authored by Shawn Lin's avatar Shawn Lin Committed by Heiko Stuebner
Browse files

arm64: dts: rockchip: Fix rk3588 PCIe range mappings 



The pcie bus address should be mapped 1:1 to the cpu side MMIO address, so
that there is no same address allocated from normal system memory. Otherwise
it's broken if the same address assigned to the EP for DMA purpose.Fix it to
sync with the vendor BSP.

Fixes: 0acf4fa7 ("arm64: dts: rockchip: add PCIe3 support for rk3588")
Fixes: 8d81b77f ("arm64: dts: rockchip: add rk3588 PCIe2 support")
Cc: stable@vger.kernel.org
Cc: Sebastian Reichel <sebastian.reichel@collabora.com>
Signed-off-by: default avatarShawn Lin <shawn.lin@rock-chips.com>
Link: https://patch.msgid.link/1767600929-195341-2-git-send-email-shawn.lin@rock-chips.com


Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent f63ea193

arch/arm64/boot/dts/rockchip/rk3588-base.dtsi

+2 −2
Original line number Diff line number Diff line
@@ -2019,7 +2019,7 @@ pcie2x1l1: pcie@fe180000 { 
		power-domains = <&power RK3588_PD_PCIE>;

		ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>,

			 <0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>,

			 <0x03000000 0x0 0x40000000 0x9 0xc0000000 0x0 0x40000000>;

			 <0x03000000 0x9 0xc0000000 0x9 0xc0000000 0x0 0x40000000>;

		reg = <0xa 0x40c00000 0x0 0x00400000>,

		      <0x0 0xfe180000 0x0 0x00010000>,

		      <0x0 0xf3000000 0x0 0x00100000>;
@@ -2071,7 +2071,7 @@ pcie2x1l2: pcie@fe190000 { 
		power-domains = <&power RK3588_PD_PCIE>;

		ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,

			 <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>,

			 <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>;

			 <0x03000000 0xa 0x00000000 0xa 0x00000000 0x0 0x40000000>;

		reg = <0xa 0x41000000 0x0 0x00400000>,

		      <0x0 0xfe190000 0x0 0x00010000>,

		      <0x0 0xf4000000 0x0 0x00100000>;

arch/arm64/boot/dts/rockchip/rk3588-extra.dtsi

+3 −3
Original line number Diff line number Diff line
@@ -375,7 +375,7 @@ pcie3x4: pcie@fe150000 { 
		power-domains = <&power RK3588_PD_PCIE>;

		ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>,

			 <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>,

			 <0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>;

			 <0x03000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>;

		reg = <0xa 0x40000000 0x0 0x00400000>,

		      <0x0 0xfe150000 0x0 0x00010000>,

		      <0x0 0xf0000000 0x0 0x00100000>;
@@ -462,7 +462,7 @@ pcie3x2: pcie@fe160000 { 
		power-domains = <&power RK3588_PD_PCIE>;

		ranges = <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>,

			 <0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>,

			 <0x03000000 0x0 0x40000000 0x9 0x40000000 0x0 0x40000000>;

			 <0x03000000 0x9 0x40000000 0x9 0x40000000 0x0 0x40000000>;

		reg = <0xa 0x40400000 0x0 0x00400000>,

		      <0x0 0xfe160000 0x0 0x00010000>,

		      <0x0 0xf1000000 0x0 0x00100000>;
@@ -512,7 +512,7 @@ pcie2x1l0: pcie@fe170000 { 
		power-domains = <&power RK3588_PD_PCIE>;

		ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>,

			 <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x00e00000>,

			 <0x03000000 0x0 0x40000000 0x9 0x80000000 0x0 0x40000000>;

			 <0x03000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>;

		reg = <0xa 0x40800000 0x0 0x00400000>,

		      <0x0 0xfe170000 0x0 0x00010000>,

		      <0x0 0xf2000000 0x0 0x00100000>;