Commit 473b6276 authored by Fei Yang's avatar Fei Yang Committed by Rodrigo Vivi
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drm/xe: explicitly set GGTT access for GuC DMA 



Confirmed with hardware that setting GGTT memory access for GuC
firmware loading is correct for all platforms and required for
new platforms going forward.

Signed-off-by: default avatarFei Yang <fei.yang@intel.com>
Reviewed-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
Link: https://lore.kernel.org/r/20231122204501.1353325-2-fei.yang@intel.com


Signed-off-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
parent e1fbc4f1

drivers/gpu/drm/xe/regs/xe_guc_regs.h

+1 −0
Original line number Diff line number Diff line
@@ -70,6 +70,7 @@ 
#define DMA_ADDR_1_HIGH				XE_REG(0xc30c)

#define   DMA_ADDR_SPACE_MASK			REG_GENMASK(20, 16)

#define   DMA_ADDRESS_SPACE_WOPCM		REG_FIELD_PREP(DMA_ADDR_SPACE_MASK, 7)

#define   DMA_ADDRESS_SPACE_GGTT		REG_FIELD_PREP(DMA_ADDR_SPACE_MASK, 8)

#define DMA_COPY_SIZE				XE_REG(0xc310)

#define DMA_CTRL				XE_REG(0xc314)

#define   HUC_UKERNEL				REG_BIT(9)

drivers/gpu/drm/xe/xe_uc_fw.c

+2 −1
Original line number Diff line number Diff line
@@ -746,7 +746,8 @@ static int uc_fw_xfer(struct xe_uc_fw *uc_fw, u32 offset, u32 dma_flags) 
	/* Set the source address for the uCode */

	src_offset = uc_fw_ggtt_offset(uc_fw) + uc_fw->css_offset;

	xe_mmio_write32(gt, DMA_ADDR_0_LOW, lower_32_bits(src_offset));

	xe_mmio_write32(gt, DMA_ADDR_0_HIGH, upper_32_bits(src_offset));

	xe_mmio_write32(gt, DMA_ADDR_0_HIGH,

			upper_32_bits(src_offset) | DMA_ADDRESS_SPACE_GGTT);



	/* Set the DMA destination */

	xe_mmio_write32(gt, DMA_ADDR_1_LOW, offset);