Commit 47f3f5a8 authored by Nuno Sa's avatar Nuno Sa Committed by Stephen Boyd
Browse files

dt-bindings: clock: axi-clkgen: include AXI clk 



In order to access the registers of the HW, we need to make sure that
the AXI bus clock is enabled. Hence let's increase the number of clocks
by one and add clock-names to differentiate between parent clocks and
the bus clock.

Fixes: 0e646c52 ("clk: Add axi-clkgen driver")
Signed-off-by: default avatarNuno Sa <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20241029-axi-clkgen-fix-axiclk-v2-1-bc5e0733ad76@analog.com


Reviewed-by: default avatarConor Dooley <conor.dooley@microchip.com>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 9852d85e

Documentation/devicetree/bindings/clock/adi,axi-clkgen.yaml

+18 −4
Original line number Diff line number Diff line
@@ -26,9 +26,21 @@ properties: 
    description:

      Specifies the reference clock(s) from which the output frequency is

      derived. This must either reference one clock if only the first clock

      input is connected or two if both clock inputs are connected.

    minItems: 1

    maxItems: 2

      input is connected or two if both clock inputs are connected. The last

      clock is the AXI bus clock that needs to be enabled so we can access the

      core registers.

    minItems: 2

    maxItems: 3



  clock-names:

    oneOf:

      - items:

          - const: clkin1

          - const: s_axi_aclk

      - items:

          - const: clkin1

          - const: clkin2

          - const: s_axi_aclk



  '#clock-cells':

    const: 0
@@ -40,6 +52,7 @@ required: 
  - compatible

  - reg

  - clocks

  - clock-names

  - '#clock-cells'



additionalProperties: false
@@ -50,5 +63,6 @@ examples: 
      compatible = "adi,axi-clkgen-2.00.a";

      #clock-cells = <0>;

      reg = <0xff000000 0x1000>;

      clocks = <&osc 1>;

      clocks = <&osc 1>, <&clkc 15>;

      clock-names = "clkin1", "s_axi_aclk";

    };