Commit 48ba4a6d authored by Lucas De Marchi's avatar Lucas De Marchi
Browse files

drm/i915: Update IP_VER(12, 50) 



With no platform using graphics/media IP_VER(12, 50), replace the
checks throughout the code with IP_VER(12, 55) so the code makes sense
by itself with no additional explanation of previous baggage.

Reviewed-by: default avatarRodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: default avatarTvrtko Ursulin <tursulin@ursulin.net>
Link: https://patchwork.freedesktop.org/patch/msgid/20240320060543.4034215-5-lucas.demarchi@intel.com


Signed-off-by: default avatarLucas De Marchi <lucas.demarchi@intel.com>
parent b183bdf2

drivers/gpu/drm/i915/gem/selftests/huge_pages.c

+2 −2
Original line number Diff line number Diff line
@@ -713,7 +713,7 @@ static int igt_ppgtt_huge_fill(void *arg) 
{

	struct drm_i915_private *i915 = arg;

	unsigned int supported = RUNTIME_INFO(i915)->page_sizes;

	bool has_pte64 = GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50);

	bool has_pte64 = GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55);

	struct i915_address_space *vm;

	struct i915_gem_context *ctx;

	unsigned long max_pages;
@@ -857,7 +857,7 @@ static int igt_ppgtt_huge_fill(void *arg) 
static int igt_ppgtt_64K(void *arg)

{

	struct drm_i915_private *i915 = arg;

	bool has_pte64 = GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50);

	bool has_pte64 = GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55);

	struct drm_i915_gem_object *obj;

	struct i915_address_space *vm;

	struct i915_gem_context *ctx;

drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c

+4 −4
Original line number Diff line number Diff line
@@ -117,7 +117,7 @@ static bool fastblit_supports_x_tiling(const struct drm_i915_private *i915) 
	if (gen < 12)

		return true;



	if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))

	if (GRAPHICS_VER_FULL(i915) < IP_VER(12, 55))

		return false;



	return HAS_DISPLAY(i915);
@@ -166,7 +166,7 @@ static int prepare_blit(const struct tiled_blits *t, 
		src_pitch = t->width; /* in dwords */

		if (src->tiling == CLIENT_TILING_Y) {

			src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(YMAJOR);

			if (GRAPHICS_VER_FULL(to_i915(batch->base.dev)) >= IP_VER(12, 50))

			if (GRAPHICS_VER_FULL(to_i915(batch->base.dev)) >= IP_VER(12, 55))

				src_4t = XY_FAST_COPY_BLT_D1_SRC_TILE4;

		} else if (src->tiling == CLIENT_TILING_X) {

			src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(TILE_X);
@@ -177,7 +177,7 @@ static int prepare_blit(const struct tiled_blits *t, 
		dst_pitch = t->width; /* in dwords */

		if (dst->tiling == CLIENT_TILING_Y) {

			dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(YMAJOR);

			if (GRAPHICS_VER_FULL(to_i915(batch->base.dev)) >= IP_VER(12, 50))

			if (GRAPHICS_VER_FULL(to_i915(batch->base.dev)) >= IP_VER(12, 55))

				dst_4t = XY_FAST_COPY_BLT_D1_DST_TILE4;

		} else if (dst->tiling == CLIENT_TILING_X) {

			dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(TILE_X);
@@ -365,7 +365,7 @@ static u64 tiled_offset(const struct intel_gt *gt, 
		v += x;



		swizzle = gt->ggtt->bit_6_swizzle_x;

	} else if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 50)) {

	} else if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 55)) {

		/* Y-major tiling layout is Tile4 for Xe_HP and beyond */

		v = linear_x_y_to_ftiled_pos(x_pos, y_pos, stride, 32);

drivers/gpu/drm/i915/gt/gen8_engine_cs.c

+1 −1
Original line number Diff line number Diff line
@@ -827,7 +827,7 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs) 
		cs = gen12_emit_pipe_control(cs, 0,

					     PIPE_CONTROL_DEPTH_CACHE_FLUSH, 0);



	if (GRAPHICS_VER(i915) == 12 && GRAPHICS_VER_FULL(i915) < IP_VER(12, 50))

	if (GRAPHICS_VER(i915) == 12 && GRAPHICS_VER_FULL(i915) < IP_VER(12, 55))

		/* Wa_1409600907 */

		flags |= PIPE_CONTROL_DEPTH_STALL;

drivers/gpu/drm/i915/gt/intel_engine_cs.c

+2 −3
Original line number Diff line number Diff line
@@ -765,14 +765,14 @@ static void engine_mask_apply_media_fuses(struct intel_gt *gt) 
	 * and bits have disable semantices.

	 */

	media_fuse = intel_uncore_read(gt->uncore, GEN11_GT_VEBOX_VDBOX_DISABLE);

	if (MEDIA_VER_FULL(i915) < IP_VER(12, 50))

	if (MEDIA_VER_FULL(i915) < IP_VER(12, 55))

		media_fuse = ~media_fuse;



	vdbox_mask = media_fuse & GEN11_GT_VDBOX_DISABLE_MASK;

	vebox_mask = (media_fuse & GEN11_GT_VEBOX_DISABLE_MASK) >>

		      GEN11_GT_VEBOX_DISABLE_SHIFT;



	if (MEDIA_VER_FULL(i915) >= IP_VER(12, 50)) {

	if (MEDIA_VER_FULL(i915) >= IP_VER(12, 55)) {

		fuse1 = intel_uncore_read(gt->uncore, HSW_PAVP_FUSE1);

		gt->info.sfc_mask = REG_FIELD_GET(XEHP_SFC_ENABLE_MASK, fuse1);

	} else {
@@ -1193,7 +1193,6 @@ static int intel_engine_init_tlb_invalidation(struct intel_engine_cs *engine) 
		if (GRAPHICS_VER_FULL(i915) == IP_VER(12, 74) ||

		    GRAPHICS_VER_FULL(i915) == IP_VER(12, 71) ||

		    GRAPHICS_VER_FULL(i915) == IP_VER(12, 70) ||

		    GRAPHICS_VER_FULL(i915) == IP_VER(12, 50) ||

		    GRAPHICS_VER_FULL(i915) == IP_VER(12, 55)) {

			regs = xehp_regs;

			num = ARRAY_SIZE(xehp_regs);

drivers/gpu/drm/i915/gt/intel_execlists_submission.c

+5 −5
Original line number Diff line number Diff line
@@ -493,7 +493,7 @@ __execlists_schedule_in(struct i915_request *rq) 
		/* Use a fixed tag for OA and friends */

		GEM_BUG_ON(ce->tag <= BITS_PER_LONG);

		ce->lrc.ccid = ce->tag;

	} else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50)) {

	} else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55)) {

		/* We don't need a strict matching tag, just different values */

		unsigned int tag = ffs(READ_ONCE(engine->context_tag));
@@ -613,7 +613,7 @@ static void __execlists_schedule_out(struct i915_request * const rq, 
		intel_engine_add_retire(engine, ce->timeline);



	ccid = ce->lrc.ccid;

	if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50)) {

	if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55)) {

		ccid >>= XEHP_SW_CTX_ID_SHIFT - 32;

		ccid &= XEHP_MAX_CONTEXT_HW_ID;

	} else {
@@ -1907,7 +1907,7 @@ process_csb(struct intel_engine_cs *engine, struct i915_request **inactive) 
		ENGINE_TRACE(engine, "csb[%d]: status=0x%08x:0x%08x\n",

			     head, upper_32_bits(csb), lower_32_bits(csb));



		if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))

		if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))

			promote = xehp_csb_parse(csb);

		else if (GRAPHICS_VER(engine->i915) >= 12)

			promote = gen12_csb_parse(csb);
@@ -3479,7 +3479,7 @@ logical_ring_default_vfuncs(struct intel_engine_cs *engine) 
		}

	}



	if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50)) {

	if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55)) {

		if (intel_engine_has_preemption(engine))

			engine->emit_bb_start = xehp_emit_bb_start;

		else
@@ -3582,7 +3582,7 @@ int intel_execlists_submission_setup(struct intel_engine_cs *engine) 


	engine->context_tag = GENMASK(BITS_PER_LONG - 2, 0);

	if (GRAPHICS_VER(engine->i915) >= 11 &&

	    GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 50)) {

	    GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 55)) {

		execlists->ccid |= engine->instance << (GEN11_ENGINE_INSTANCE_SHIFT - 32);

		execlists->ccid |= engine->class << (GEN11_ENGINE_CLASS_SHIFT - 32);

	}