Unverified Commit 490be7ba authored by Vijendar Mukunda's avatar Vijendar Mukunda Committed by Mark Brown
Browse files

ASoC: SOF: amd: add support for acp7.0 based platform 



Add SOF support for ACP7.0 version based platform.

Signed-off-by: default avatarVijendar Mukunda <Vijendar.Mukunda@amd.com>
Reviewed-by: default avatarPierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://patch.msgid.link/20240823053739.465187-3-Vijendar.Mukunda@amd.com


Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent e17de785

sound/soc/sof/amd/Kconfig

+10 −0
Original line number Diff line number Diff line
@@ -88,4 +88,14 @@ config SND_SOC_SOF_AMD_ACP63 
	  AMD ACP6.3 version based platforms.

	  Say Y if you want to enable SOF on ACP6.3 based platform.

	  If unsure select "N".



config SND_SOC_SOF_AMD_ACP70

	tristate "SOF support for ACP7.0 platform"

	depends on SND_SOC_SOF_PCI

	select SND_SOC_SOF_AMD_COMMON

	help

	  Select this option for SOF support on

	  AMD ACP7.0 version based platforms.

	  Say Y if you want to enable SOF on ACP7.0 based platform.



endif

sound/soc/sof/amd/Makefile

+3 −1
Original line number Diff line number Diff line
@@ -2,7 +2,7 @@ 
# This file is provided under a dual BSD/GPLv2 license. When using or

# redistributing this file, you may do so under either license.

#

# Copyright(c) 2021, 2023 Advanced Micro Devices, Inc. All rights reserved.

# Copyright(c) 2021, 2023, 2024 Advanced Micro Devices, Inc. All rights reserved.



snd-sof-amd-acp-y := acp.o acp-loader.o acp-ipc.o acp-pcm.o acp-stream.o acp-trace.o acp-common.o

snd-sof-amd-acp-$(CONFIG_SND_SOC_SOF_ACP_PROBES) += acp-probes.o
@@ -10,9 +10,11 @@ snd-sof-amd-renoir-y := pci-rn.o renoir.o 
snd-sof-amd-rembrandt-y := pci-rmb.o rembrandt.o

snd-sof-amd-vangogh-y := pci-vangogh.o vangogh.o

snd-sof-amd-acp63-y := pci-acp63.o acp63.o

snd-sof-amd-acp70-y := pci-acp70.o acp70.o



obj-$(CONFIG_SND_SOC_SOF_AMD_COMMON) += snd-sof-amd-acp.o

obj-$(CONFIG_SND_SOC_SOF_AMD_RENOIR) += snd-sof-amd-renoir.o

obj-$(CONFIG_SND_SOC_SOF_AMD_REMBRANDT) += snd-sof-amd-rembrandt.o

obj-$(CONFIG_SND_SOC_SOF_AMD_VANGOGH) += snd-sof-amd-vangogh.o

obj-$(CONFIG_SND_SOC_SOF_AMD_ACP63) += snd-sof-amd-acp63.o

obj-$(CONFIG_SND_SOC_SOF_AMD_ACP70) += snd-sof-amd-acp70.o

sound/soc/sof/amd/acp-dsp-offset.h

+23 −1
Original line number Diff line number Diff line
@@ -3,7 +3,7 @@ 
 * This file is provided under a dual BSD/GPLv2 license. When using or

 * redistributing this file, you may do so under either license.

 *

 * Copyright(c) 2021, 2023 Advanced Micro Devices, Inc. All rights reserved.

 * Copyright(c) 2021, 2023, 2024 Advanced Micro Devices, Inc. All rights reserved.

 *

 * Author: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>

 */
@@ -23,6 +23,17 @@ 
#define ACP_DMA_CH_STS				0xE8

#define ACP_DMA_CH_GROUP			0xEC

#define ACP_DMA_CH_RST_STS			0xF0

#define ACP70_DMA_CNTL_0			0x00

#define ACP70_DMA_DSCR_STRT_IDX_0		0x28

#define ACP70_DMA_DSCR_CNT_0			0x50

#define ACP70_DMA_PRIO_0			0x78

#define ACP70_DMA_CUR_DSCR_0			0xA0

#define ACP70_DMA_ERR_STS_0			0xF0

#define ACP70_DMA_DESC_BASE_ADDR		0x118

#define ACP70_DMA_DESC_MAX_NUM_DSCR		0x11C

#define ACP70_DMA_CH_STS			0x120

#define ACP70_DMA_CH_GROUP			0x124

#define ACP70_DMA_CH_RST_STS			0x128



/* Registers from ACP_DSP_0 block */

#define ACP_DSP0_RUNSTALL			0x414
@@ -56,11 +67,13 @@ 
#define ACP3X_PGFSM_BASE			0x141C

#define ACP5X_PGFSM_BASE			0x1424

#define ACP6X_PGFSM_BASE                        0x1024

#define ACP70_PGFSM_BASE                        ACP6X_PGFSM_BASE

#define PGFSM_CONTROL_OFFSET			0x0

#define PGFSM_STATUS_OFFSET			0x4

#define ACP3X_CLKMUX_SEL			0x1424

#define ACP5X_CLKMUX_SEL			0x142C

#define ACP6X_CLKMUX_SEL			0x102C

#define ACP70_CLKMUX_SEL			ACP6X_CLKMUX_SEL



/* Registers from ACP_INTR block */

#define ACP3X_EXT_INTR_STAT			0x1808
@@ -69,22 +82,30 @@ 
#define ACP6X_EXTERNAL_INTR_CNTL		0x1A04

#define ACP6X_EXT_INTR_STAT                     0x1A0C

#define ACP6X_EXT_INTR_STAT1			0x1A10

#define ACP70_EXTERNAL_INTR_ENB			ACP6X_EXTERNAL_INTR_ENB

#define ACP70_EXTERNAL_INTR_CNTL		ACP6X_EXTERNAL_INTR_CNTL

#define ACP70_EXT_INTR_STAT			ACP6X_EXT_INTR_STAT

#define ACP70_EXT_INTR_STAT1			ACP6X_EXT_INTR_STAT1



#define ACP3X_DSP_SW_INTR_BASE			0x1814

#define ACP5X_DSP_SW_INTR_BASE			0x1814

#define ACP6X_DSP_SW_INTR_BASE                  0x1808

#define ACP70_DSP_SW_INTR_BASE			ACP6X_DSP_SW_INTR_BASE

#define DSP_SW_INTR_CNTL_OFFSET			0x0

#define DSP_SW_INTR_STAT_OFFSET			0x4

#define DSP_SW_INTR_TRIG_OFFSET			0x8

#define ACP3X_ERROR_STATUS			0x18C4

#define ACP6X_ERROR_STATUS			0x1A4C

#define ACP70_ERROR_STATUS			ACP6X_ERROR_STATUS

#define ACP3X_AXI2DAGB_SEM_0			0x1880

#define ACP5X_AXI2DAGB_SEM_0			0x1884

#define ACP6X_AXI2DAGB_SEM_0			0x1874

#define ACP70_AXI2DAGB_SEM_0			ACP6X_AXI2DAGB_SEM_0



/* ACP common registers to report errors related to I2S & SoundWire interfaces */

#define ACP3X_SW_I2S_ERROR_REASON		0x18C8

#define ACP6X_SW0_I2S_ERROR_REASON		0x18B4

#define ACP7X_SW0_I2S_ERROR_REASON		ACP6X_SW0_I2S_ERROR_REASON

#define ACP_SW1_I2S_ERROR_REASON		0x1A50



/* Registers from ACP_SHA block */
@@ -101,6 +122,7 @@ 


#define ACP_SCRATCH_REG_0			0x10000

#define ACP6X_DSP_FUSION_RUNSTALL		0x0644

#define ACP70_DSP_FUSION_RUNSTALL		ACP6X_DSP_FUSION_RUNSTALL



/* Cache window registers */

#define ACP_DSP0_CACHE_OFFSET0			0x0420

sound/soc/sof/amd/acp.c

+53 −12
Original line number Diff line number Diff line
@@ -64,13 +64,24 @@ static void init_dma_descriptor(struct acp_dev_data *adata) 
{

	struct snd_sof_dev *sdev = adata->dev;

	const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);

	struct acp_dev_data *acp_data = sdev->pdata->hw_pdata;

	unsigned int addr;

	unsigned int acp_dma_desc_base_addr, acp_dma_desc_max_num_dscr;



	addr = desc->sram_pte_offset + sdev->debug_box.offset +

	       offsetof(struct scratch_reg_conf, dma_desc);



	snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_DESC_BASE_ADDR, addr);

	snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_DESC_MAX_NUM_DSCR, ACP_MAX_DESC_CNT);

	switch (acp_data->pci_rev) {

	case ACP70_PCI_ID:

		acp_dma_desc_base_addr = ACP70_DMA_DESC_BASE_ADDR;

		acp_dma_desc_max_num_dscr = ACP70_DMA_DESC_MAX_NUM_DSCR;

		break;

	default:

		acp_dma_desc_base_addr = ACP_DMA_DESC_BASE_ADDR;

		acp_dma_desc_max_num_dscr = ACP_DMA_DESC_MAX_NUM_DSCR;

	}

	snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_desc_base_addr, addr);

	snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_desc_max_num_dscr, ACP_MAX_DESC_CNT);

}



static void configure_dma_descriptor(struct acp_dev_data *adata, unsigned short idx,
@@ -92,29 +103,51 @@ static int config_dma_channel(struct acp_dev_data *adata, unsigned int ch, 
			      unsigned int idx, unsigned int dscr_count)

{

	struct snd_sof_dev *sdev = adata->dev;

	struct acp_dev_data *acp_data = sdev->pdata->hw_pdata;

	const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);

	unsigned int val, status;

	unsigned int acp_dma_cntl_0, acp_dma_ch_rst_sts, acp_dma_dscr_err_sts_0;

	unsigned int acp_dma_dscr_cnt_0, acp_dma_prio_0, acp_dma_dscr_strt_idx_0;

	int ret;



	snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_CNTL_0 + ch * sizeof(u32),

	switch (acp_data->pci_rev) {

	case ACP70_PCI_ID:

		acp_dma_cntl_0 = ACP70_DMA_CNTL_0;

		acp_dma_ch_rst_sts = ACP70_DMA_CH_RST_STS;

		acp_dma_dscr_err_sts_0 = ACP70_DMA_ERR_STS_0;

		acp_dma_dscr_cnt_0 = ACP70_DMA_DSCR_CNT_0;

		acp_dma_prio_0 = ACP70_DMA_PRIO_0;

		acp_dma_dscr_strt_idx_0 = ACP70_DMA_DSCR_STRT_IDX_0;

		break;

	default:

		acp_dma_cntl_0 = ACP_DMA_CNTL_0;

		acp_dma_ch_rst_sts = ACP_DMA_CH_RST_STS;

		acp_dma_dscr_err_sts_0 = ACP_DMA_ERR_STS_0;

		acp_dma_dscr_cnt_0 = ACP_DMA_DSCR_CNT_0;

		acp_dma_prio_0 = ACP_DMA_PRIO_0;

		acp_dma_dscr_strt_idx_0 = ACP_DMA_DSCR_STRT_IDX_0;

	}



	snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_cntl_0 + ch * sizeof(u32),

			  ACP_DMA_CH_RST | ACP_DMA_CH_GRACEFUL_RST_EN);



	ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_DMA_CH_RST_STS, val,

	ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, acp_dma_ch_rst_sts, val,

					    val & (1 << ch), ACP_REG_POLL_INTERVAL,

					    ACP_REG_POLL_TIMEOUT_US);

	if (ret < 0) {

		status = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->acp_error_stat);

		val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_DMA_ERR_STS_0 + ch * sizeof(u32));

		val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, acp_dma_dscr_err_sts_0 +

				       ch * sizeof(u32));



		dev_err(sdev->dev, "ACP_DMA_ERR_STS :0x%x ACP_ERROR_STATUS :0x%x\n", val, status);

		return ret;

	}



	snd_sof_dsp_write(sdev, ACP_DSP_BAR, (ACP_DMA_CNTL_0 + ch * sizeof(u32)), 0);

	snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_DSCR_CNT_0 + ch * sizeof(u32), dscr_count);

	snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_DSCR_STRT_IDX_0 + ch * sizeof(u32), idx);

	snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_PRIO_0 + ch * sizeof(u32), 0);

	snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DMA_CNTL_0 + ch * sizeof(u32), ACP_DMA_CH_RUN);

	snd_sof_dsp_write(sdev, ACP_DSP_BAR, (acp_dma_cntl_0 + ch * sizeof(u32)), 0);

	snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_dscr_cnt_0 + ch * sizeof(u32), dscr_count);

	snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_dscr_strt_idx_0 + ch * sizeof(u32), idx);

	snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_prio_0 + ch * sizeof(u32), 0);

	snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_cntl_0 + ch * sizeof(u32), ACP_DMA_CH_RUN);



	return ret;

}
@@ -453,6 +486,10 @@ static int acp_power_on(struct snd_sof_dev *sdev) 
		acp_pgfsm_status_mask = ACP6X_PGFSM_STATUS_MASK;

		acp_pgfsm_cntl_mask = ACP6X_PGFSM_CNTL_POWER_ON_MASK;

		break;

	case ACP70_PCI_ID:

		acp_pgfsm_status_mask = ACP70_PGFSM_STATUS_MASK;

		acp_pgfsm_cntl_mask = ACP70_PGFSM_CNTL_POWER_ON_MASK;

		break;

	default:

		return -EINVAL;

	}
@@ -561,8 +598,11 @@ static bool check_acp_sdw_enable_status(struct snd_sof_dev *sdev) 


int amd_sof_acp_suspend(struct snd_sof_dev *sdev, u32 target_state)

{

	struct acp_dev_data *acp_data;

	int ret;

	bool enable = false;



	acp_data = sdev->pdata->hw_pdata;

	/* When acp_reset() function is invoked, it will apply ACP SOFT reset and

	 * DSP reset. ACP Soft reset sequence will cause all ACP IP registers will

	 * be reset to default values which will break the ClockStop Mode functionality.
@@ -577,8 +617,9 @@ int amd_sof_acp_suspend(struct snd_sof_dev *sdev, u32 target_state) 
		dev_err(sdev->dev, "ACP Reset failed\n");

		return ret;

	}



	snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_CONTROL, 0x00);

	if (acp_data->pci_rev == ACP70_PCI_ID)

		enable = true;

	snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_CONTROL, enable);



	return 0;

}

sound/soc/sof/amd/acp.h

+9 −0
Original line number Diff line number Diff line
@@ -29,6 +29,8 @@ 
#define ACP3X_PGFSM_STATUS_MASK			0x03

#define ACP6X_PGFSM_CNTL_POWER_ON_MASK		0x07

#define ACP6X_PGFSM_STATUS_MASK			0x0F

#define ACP70_PGFSM_CNTL_POWER_ON_MASK		0x1F

#define ACP70_PGFSM_STATUS_MASK			0xFF



#define ACP_POWERED_ON				0x00

#define ACP_ASSERT_RESET			0x01
@@ -42,6 +44,7 @@ 
#define ACP3X_SRAM_PTE_OFFSET			0x02050000

#define ACP5X_SRAM_PTE_OFFSET			0x02050000

#define ACP6X_SRAM_PTE_OFFSET			0x03800000

#define ACP70_SRAM_PTE_OFFSET			ACP6X_SRAM_PTE_OFFSET

#define PAGE_SIZE_4K_ENABLE			0x2

#define ACP_PAGE_SIZE				0x1000

#define ACP_DMA_CH_RUN				0x02
@@ -63,17 +66,20 @@ 
#define ACP_DRAM_BASE_ADDRESS			0x01000000

#define ACP_DRAM_PAGE_COUNT			128

#define ACP_SRAM_BASE_ADDRESS			0x3806000

#define ACP7X_SRAM_BASE_ADDRESS			0x380C000

#define ACP_DSP_TO_HOST_IRQ			0x04



#define ACP_RN_PCI_ID				0x01

#define ACP_VANGOGH_PCI_ID			0x50

#define ACP_RMB_PCI_ID				0x6F

#define ACP63_PCI_ID				0x63

#define ACP70_PCI_ID				0x70



#define HOST_BRIDGE_CZN				0x1630

#define HOST_BRIDGE_VGH				0x1645

#define HOST_BRIDGE_RMB				0x14B5

#define HOST_BRIDGE_ACP63			0x14E8

#define HOST_BRIDGE_ACP70			0x1507

#define ACP_SHA_STAT				0x8000

#define ACP_PSP_TIMEOUT_US			1000000

#define ACP_EXT_INTR_ERROR_STAT			0x20000000
@@ -326,6 +332,9 @@ int sof_rembrandt_ops_init(struct snd_sof_dev *sdev); 
extern struct snd_sof_dsp_ops sof_acp63_ops;

int sof_acp63_ops_init(struct snd_sof_dev *sdev);



extern struct snd_sof_dsp_ops sof_acp70_ops;

int sof_acp70_ops_init(struct snd_sof_dev *sdev);



struct snd_soc_acpi_mach *amd_sof_machine_select(struct snd_sof_dev *sdev);

/* Machine configuration */

int snd_amd_acp_find_config(struct pci_dev *pci);